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AVX

avx-type-4 exception class

VEX-encoded integer, logical, shuffle and cryptographic instructions without floating-point exceptions, such as VPADDD, VPSHUFB and VAESENC, which Intel's manual calls Exceptions Type 4.

Class
avx-type-4 in Intel XED
Applies to
VEX encodings, 128 and 256 bits, including those of AES-NI, GFNI, PCLMULQDQ, SM3 and the VEX-encoded VNNI, IFMA and NE-CONVERT instructions.
Instructions
170 mnemonics, 629 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no VEX prefix.
#UDThe operating system has not enabled the AVX state: CR4.OSXSAVE is 0, or XCR0 bits 1 and 2 (SSE and AVX state) are not both 1.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the VEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.

Notes

The VEX forms accept any alignment: the table’s 16-byte rule is for the legacy encoding (SSE_TYPE_4). The class has neither #XM nor #AC.

Two tables of the manual add reasons for #UD to single instructions of the class:

  • Table 2-16: VBLENDVPD, VBLENDVPS, VPBLENDVB, VTESTPD, VTESTPS, VPBLENDD, VPERMD, VPERMPS and VPSRAVD raise #UD when VEX.W is 1.
  • Table 2-17: the 256-bit forms of the integer instructions need AVX2, and VPCMPESTRI, VPCMPESTRM, VPCMPISTRI, VPCMPISTRM and VPHMINPOSUW have no 256-bit form at all.

VMASKMOVDQU also raises #UD for VEX.L = 1 or for a VEX.vvvv other than 1111b, and stores to an address that need not be aligned.

  • SSE_TYPE_4: Legacy SSE instructions with a 16-byte memory operand and no floating-point exceptions, such as PADDD, PSHUFB, ANDPS and AESENC, which Intel's manual calls Exceptions Type 4.
  • avx-type-4M: The VEX-encoded unaligned moves VMOVUPS, VMOVUPD and VMOVDQU, which Intel's manual refers to Exceptions Type 4 with one more reason for #UD.
  • avx-type-6: VEX-encoded instructions without a legacy SSE form, such as VBROADCASTSS, VINSERTF128, VPERM2I128 and VMASKMOVPS, which Intel's manual calls Exceptions Type 6.
  • avx-type-7: VEX-encoded instructions without a memory operand or floating-point exceptions, such as VMOVMSKPS, VPSRLDQ and the shifts by an immediate count, which Intel's manual calls Exceptions Type 7.
  • AVX512-E4: EVEX-encoded integer, logical and other instructions without floating-point exceptions, such as VPADDD, VPTERNLOGD and VMOVDQU32, with memory fault suppression, which Intel's manual calls Exceptions Type E4.

Instructions

Intel XED puts forms of 170 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX

AVX2

AVX-VNNI

AVX-VNNI-INT8

AVX-VNNI-INT16

AVX-IFMA

AVX-NE-CONVERT

AES-NI

GFNI

VAES

VPCLMULQDQ

SM3

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.4, Table 2-21; Section 2.5, Tables 2-14 to 2-17; Chapter 4, MASKMOVDQU.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.