avx-type-4M exception class

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.

Exception	Real	Virtual-8086	Protected	64-bit	Condition
`#UD`	yes	yes	no	no	Always: real and virtual-8086 mode have no VEX prefix.
`#UD`	no	no	yes	yes	The operating system has not enabled the AVX state: `CR4.OSXSAVE` is 0, or `XCR0` bits 1 and 2 (SSE and AVX state) are not both 1.
`#UD`	yes	yes	yes	yes	The instruction has a LOCK prefix (F0).
`#UD`	no	no	yes	yes	A REX, F2, F3 or 66 prefix comes before the VEX prefix.
`#UD`	yes	yes	yes	yes	The processor lacks the instruction’s extension: its CPUID feature flag is 0.
`#UD`	no	no	yes	yes	`VEX.vvvv` is not 1111b: these moves have no second source register.
`#NM`	yes	yes	yes	yes	`CR0.TS` (task switched, bit 3) is 1.
`#SS(0)`	no	no	yes	no	A memory operand addressed through SS lies outside the stack segment.
`#SS(0)`	no	no	no	yes	A memory operand addressed through SS has a non-canonical address.
`#GP(0)`	no	no	yes	no	A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
`#GP(0)`	no	no	no	yes	A memory operand has a non-canonical address.
`#GP(0)`	yes	yes	no	no	A memory operand extends past offset FFFFh of its segment.
`#PF(fault-code)`	no	yes	yes	yes	Accessing a memory operand causes a page fault.

Notes

XED gives the unaligned moves a class of their own. Their memory operand may have any alignment, and the pages of the manual add #UD for an unused VEX.vvvv field that is not 1111b.

The pages of VMOVUPS and VMOVUPD note that their treatment of #AC varies, although the Type 4 table has no #AC row.

Instructions

Intel XED puts forms of 3 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

Exception conditions

Notes

Related classes

Instructions

AVX

Sources