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AVX

avx-type-5 exception class

VEX-encoded moves, inserts, extracts and conversions on operands smaller than 16 bytes without floating-point exceptions, such as VMOVD, VPINSRB and VPMOVZXBW, which Intel's manual calls Exceptions Type 5.

Class
avx-type-5 in Intel XED
Applies to
VEX encodings, including VSTMXCSR.
Instructions
37 mnemonics, 114 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no VEX prefix.
#UDThe operating system has not enabled the AVX state: CR4.OSXSAVE is 0, or XCR0 bits 1 and 2 (SSE and AVX state) are not both 1.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the VEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.
#AC(0)Code at privilege level 3 makes a misaligned 2-, 4- or 8-byte memory access while alignment checking is on.

Notes

There is no alignment rule for #GP and no #XM; a misaligned memory operand raises #AC(0) only when alignment checking is on at privilege level 3.

Many of these instructions exist only as 128-bit forms and raise #UD when VEX.L is 1 (Table 2-17): VEXTRACTPS, VINSERTPS, VMOVD, VMOVQ, VMOVLPD, VMOVLPS, VMOVHPD, VMOVHPS, VPEXTRB, VPEXTRW, VPEXTRD, VPEXTRQ, VPINSRB, VPINSRW, VPINSRD, VPINSRQ and VSTMXCSR. VLDMXCSR, which the manual lists here too, has a class of its own in XED (avx-type-5L).

  • SSE_TYPE_5: Legacy SSE moves, inserts, extracts and conversions on operands smaller than 16 bytes without floating-point exceptions, such as MOVD, PINSRW and PMOVZXBW, which Intel's manual calls Exceptions Type 5.
  • avx-type-3: VEX-encoded floating-point arithmetic on scalars and other operands smaller than 16 bytes, such as VADDSS, VCOMISD and the scalar FMA instructions, which Intel's manual calls Exceptions Type 3.
  • avx-type-5L: VLDMXCSR, which loads the MXCSR register from memory, with the conditions of Exceptions Type 5 of Intel's manual and a #GP for reserved bits.
  • AVX512-E5: EVEX-encoded instructions that read part of a vector or a scalar from memory, such as VPMOVZXBD and VCVTDQ2PD, with memory fault suppression, which Intel's manual calls Exceptions Type E5.
  • AVX512-E9NF: EVEX-encoded 128-bit moves, inserts and extracts of single elements, such as VMOVD, VPEXTRW and VINSERTPS, without fault suppression, which Intel's manual calls Exceptions Type E9NF.

Instructions

Intel XED puts forms of 37 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX

AVX2

AVX-NE-CONVERT

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.5, Table 2-22; Section 2.5, Tables 2-14, 2-15 and 2-17.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.