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AVX

avx-type-5L exception class

VLDMXCSR, which loads the MXCSR register from memory, with the conditions of Exceptions Type 5 of Intel's manual and a #GP for reserved bits.

Class
avx-type-5L in Intel XED
Applies to
The VEX encoding of VLDMXCSR, VEX.LZ.0F.WIG AE /2.
Instructions
1 mnemonic, 1 form
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no VEX prefix.
#UDThe operating system has not enabled the AVX state: CR4.OSXSAVE is 0, or XCR0 bits 1 and 2 (SSE and AVX state) are not both 1.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the VEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#UDVEX.L is 1, or VEX.vvvv is not 1111b.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GPThe loaded value sets a reserved bit of MXCSR.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.
#AC(0)Code at privilege level 3 makes a misaligned 2-, 4- or 8-byte memory access while alignment checking is on.

Notes

XED gives VLDMXCSR a class of its own; the legacy LDMXCSR, which raises the same #GP for reserved bits, is SSE_TYPE_5 in XED. The manual writes this exception as #GP, without an error code.

A new MXCSR value that unmasks an exception whose flag is already set raises nothing at once: the exception comes with the next instruction that operates on XMM or YMM registers and reports that exception.

  • avx-type-5: VEX-encoded moves, inserts, extracts and conversions on operands smaller than 16 bytes without floating-point exceptions, such as VMOVD, VPINSRB and VPMOVZXBW, which Intel's manual calls Exceptions Type 5.
  • SSE_TYPE_5: Legacy SSE moves, inserts, extracts and conversions on operands smaller than 16 bytes without floating-point exceptions, such as MOVD, PINSRW and PMOVZXBW, which Intel's manual calls Exceptions Type 5.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.5, Table 2-22; Section 2.5, Table 2-17; Chapter 3, LDMXCSR.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.