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AVX-512

AVX512-E1 exception class

The EVEX-encoded aligned moves VMOVAPS, VMOVAPD, VMOVDQA32 and VMOVDQA64, whose memory operand must be aligned to its full size, which Intel's manual calls Exceptions Type E1.

Class
AVX512-E1 in Intel XED
Applies to
EVEX encodings, 128 to 512 bits.
Instructions
4 mnemonics, 36 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no EVEX prefix.
#UDThe operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7).
#UDAn EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the EVEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)An element that the mask enables lies outside the stack segment (a memory operand addressed through SS).
#SS(0)An element that the mask enables has a non-canonical address (a memory operand addressed through SS).
#GP(0)The memory operand is not aligned to its size: 64 bytes for EVEX.512, 32 bytes for EVEX.256, 16 bytes for EVEX.128.
#GP(0)An element that the mask enables has an effective address that its segment (CS, DS, ES, FS or GS) does not allow, such as one beyond the limit.
#GP(0)An element that the mask enables has a non-canonical address.
#GP(0)An element that the mask enables extends past offset FFFFh of its segment.
#PF(fault-code)Accessing an element that the mask enables causes a page fault.

Notes

Memory faults come only from the elements that the mask enables: a masked-off element may lie in an unmapped page without a fault, which the manual calls memory fault suppression. The alignment row of the manual’s table does not depend on the mask: the whole operand must be aligned to its size.

The class has neither #AC nor SIMD floating-point exceptions. The non-temporal moves follow the same alignment rule without fault suppression (AVX512-E1NF).

  • AVX512-E1NF: The EVEX-encoded non-temporal moves VMOVNTPS, VMOVNTPD, VMOVNTDQ and VMOVNTDQA, aligned and without fault suppression, which Intel's manual calls Exceptions Type E1NF.
  • avx-type-1: VEX-encoded moves whose memory operand must be aligned to its full size, such as VMOVAPS and VMOVNTDQ, which Intel's manual calls Exceptions Type 1.
  • AVX512-E4: EVEX-encoded integer, logical and other instructions without floating-point exceptions, such as VPADDD, VPTERNLOGD and VMOVDQU32, with memory fault suppression, which Intel's manual calls Exceptions Type E4.

Instructions

Intel XED puts forms of 4 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX10.1

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.1, Table 2-46; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 15.6.1.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.