AVX-512
AVX512-E10NF exception class
EVEX-encoded scalar instructions without floating-point exceptions or fault suppression, VCVTSI2SD and VCVTUSI2SD from 32-bit integers and VCOMISBF16, which Intel's manual calls Exceptions Type E10NF.
- Class
AVX512-E10NFin Intel XED- Applies to
- EVEX encodings of scalar instructions, which ignore the vector length.
- Instructions
- 3 mnemonics, 6 forms
- Data
- Intel XED v2026.08.23
Exception conditions
| Exception | Real | Virtual-8086 | Protected | 64-bit | Condition |
|---|---|---|---|---|---|
#UD | yes | yes | no | no | Always: real and virtual-8086 mode have no EVEX prefix. |
#UD | no | no | yes | yes | The operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7). |
#UD | no | no | yes | yes | An EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), or EVEX.b where the instruction gives it no meaning (Table 2-43). |
#UD | yes | yes | yes | yes | The instruction has a LOCK prefix (F0). |
#UD | no | no | yes | yes | A REX, F2, F3 or 66 prefix comes before the EVEX prefix. |
#UD | yes | yes | yes | yes | The processor lacks the instruction’s extension: its CPUID feature flag is 0. |
#NM | yes | yes | yes | yes | CR0.TS (task switched, bit 3) is 1. |
#SS(0) | no | no | yes | no | A memory operand addressed through SS lies outside the stack segment. |
#SS(0) | no | no | no | yes | A memory operand addressed through SS has a non-canonical address. |
#GP(0) | no | no | yes | no | A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit. |
#GP(0) | no | no | no | yes | A memory operand has a non-canonical address. |
#GP(0) | yes | yes | no | no | A memory operand extends past offset FFFFh of its segment. |
#PF(fault-code) | no | yes | yes | yes | Accessing a memory operand causes a page fault. |
#AC(0) | no | yes | yes | yes | Code at privilege level 3 makes a misaligned 2-, 4- or 8-byte memory access while alignment checking is on. |
Notes
Every 32-bit integer has an exact double-precision value, so
VCVTSI2SD and VCVTUSI2SD with a 32-bit source (EVEX.W = 0) raise
no floating-point exceptions; with a 64-bit source they are
AVX512-E3NF, as the page of
CVTSI2SD says. The BF16 compare VCOMISBF16, which the AVX10.2
specification puts here, neither raises floating-point exceptions
nor reads or updates MXCSR.
None of these instructions takes a mask. The manual’s table words its memory rows as for fault suppression; the AVX10.2 specification’s version of the table does not, and adds #GP(0) in protected mode for a memory operand addressed through DS, ES, FS or GS while that register holds a null selector.
Related classes
Instructions
Intel XED puts forms of 3 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.
AVX10.1
AVX10.2
Sources
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.9, Table 2-61; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapter 3, CVTSI2SD.
- Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026): Section 4.1 and Table 4.2; Section 7.3, VCOMISBF16.
- Intel XED v2026.08.23 (commit
0bcb6237345c): the exception class of each instruction form.
The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.