AVX-512
AVX512-E11 exception class
The EVEX-encoded half-precision conversions VCVTPH2PS and VCVTPS2PH, with memory fault suppression, which Intel's manual calls Exceptions Type E11.
- Class
AVX512-E11in Intel XED- Applies to
- The EVEX encodings of VCVTPH2PS and VCVTPS2PH.
- Instructions
- 2 mnemonics, 12 forms
- Data
- Intel XED v2026.08.23
Exception conditions
| Exception | Real | Virtual-8086 | Protected | 64-bit | Condition |
|---|---|---|---|---|---|
#UD | yes | yes | no | no | Always: real and virtual-8086 mode have no EVEX prefix. |
#UD | no | no | yes | yes | The operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7). |
#UD | no | no | yes | yes | An EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks. |
#UD | yes | yes | yes | yes | The instruction has a LOCK prefix (F0). |
#UD | no | no | yes | yes | A REX, F2, F3 or 66 prefix comes before the EVEX prefix. |
#UD | yes | yes | yes | yes | The processor lacks the instruction’s extension: its CPUID feature flag is 0. |
#NM | yes | yes | yes | yes | CR0.TS (task switched, bit 3) is 1. |
#SS(0) | no | no | yes | no | An element that the mask enables lies outside the stack segment (a memory operand addressed through SS). |
#SS(0) | no | no | no | yes | An element that the mask enables has a non-canonical address (a memory operand addressed through SS). |
#GP(0) | no | no | yes | no | An element that the mask enables has an effective address that its segment (CS, DS, ES, FS or GS) does not allow, such as one beyond the limit. |
#GP(0) | no | no | no | yes | An element that the mask enables has a non-canonical address. |
#GP(0) | yes | yes | no | no | An element that the mask enables extends past offset FFFFh of its segment. |
#PF(fault-code) | no | yes | yes | yes | Accessing an element that the mask enables causes a page fault. |
#XM | yes | yes | yes | yes | A SIMD floating-point exception that MXCSR does not mask occurs, CR4.OSXMMEXCPT is 1, and the instruction does not suppress exceptions with {sae}. |
Notes
The class has #XM, which {sae} suppresses, and memory faults come only from the elements that the mask enables. Like the VEX forms (avx-type-11), these conversions raise no #AC. The page of VCVTPS2PH adds #UD for an EVEX.vvvv other than 1111b.
Related classes
Instructions
Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.
AVX10.1
Sources
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.10, Table 2-62; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapter 5, VCVTPS2PH.
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 15.6.1.
- Intel XED v2026.08.23 (commit
0bcb6237345c): the exception class of each instruction form.
The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.