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AVX-512

AVX512-E12 exception class

The EVEX-encoded gathers and scatters, such as VGATHERDPS and VPSCATTERQQ, which Intel's manual calls Exceptions Type E12.

Class
AVX512-E12 in Intel XED
Applies to
EVEX encodings with a VSIB memory operand.
Instructions
16 mnemonics, 48 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no EVEX prefix.
#UDThe operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7).
#UDAn EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), a vector length (EVEX.L’L) that the instruction lacks, or an EVEX.vvvv other than 1111b.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the EVEX prefix.
#UDThe address size is 16 bits, which 64-bit mode does not have.
#UDThe ModR/M byte does not encode a memory operand with a SIB byte: mod is 11b or r/m is not 100b.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#UDThe mask register is k0.
#UDA gather names its destination register as its index register.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.

Notes

A gather or scatter touches only the elements whose mask bit is 1 and clears each bit as its element completes. A fault is delivered for the lowest element that faults, with every element below it complete, so the mask shows which elements remain. Neither raises #AC, and a zeroing mask ({z}) raises #UD.

Scatters write overlapping addresses in order, from the lowest element up, and other addresses in any order; a write that a later element overwrites completely may be skipped.

  • avx-type-12: The AVX2 gathers, such as VGATHERDPS and VPGATHERQQ, which load elements from the addresses in a vector of indices, the class that Intel's manual calls Exceptions Type 12.
  • AVX512-E12NP: The gather and scatter prefetches of the Xeon Phi, such as VGATHERPF0DPS and VSCATTERPF1QPD, which cannot fault, the class that Intel's manual calls Exceptions Type E12NP.

Instructions

Intel XED puts forms of 16 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX10.1

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.11, Table 2-63; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapter 5, VGATHERDPS/VGATHERQPS and VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.