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AVX-512

AVX512-E12NP exception class

The gather and scatter prefetches of the Xeon Phi, such as VGATHERPF0DPS and VSCATTERPF1QPD, which cannot fault, the class that Intel's manual calls Exceptions Type E12NP.

Class
AVX512-E12NP in Intel XED
Applies to
EVEX encodings with a VSIB memory operand (AVX512PF).
Instructions
16 mnemonics, 16 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no EVEX prefix.
#UDThe operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7).
#UDAn EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the EVEX prefix.
#UDThe address size is 16 bits, which 64-bit mode does not have.
#UDThe ModR/M byte does not encode a memory operand with a SIB byte: mod is 11b or r/m is not 100b.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#UDThe mask register is k0.
#NMCR0.TS (task switched, bit 3) is 1.

Notes

The prefetches are hints: the elements with a mask bit of 1 are prefetched in any order, or not at all, and the mask stays as it was. They cause neither memory faults nor floating-point exceptions, so the class has only #UD and #NM.

  • AVX512-E12: The EVEX-encoded gathers and scatters, such as VGATHERDPS and VPSCATTERQQ, which Intel's manual calls Exceptions Type E12.

Instructions

Intel XED puts forms of 16 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX512PF

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.11, Table 2-64; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapter 8, VGATHERPF0DPS and the other sparse prefetches.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.