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AVX-512

AVX512-E4 exception class

EVEX-encoded integer, logical and other instructions without floating-point exceptions, such as VPADDD, VPTERNLOGD and VMOVDQU32, with memory fault suppression, which Intel's manual calls Exceptions Type E4.

Class
AVX512-E4 in Intel XED
Applies to
EVEX encodings, 128 to 512 bits.
Instructions
254 mnemonics, 1,520 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no EVEX prefix.
#UDThe operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7).
#UDAn EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the EVEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)An element that the mask enables lies outside the stack segment (a memory operand addressed through SS).
#SS(0)An element that the mask enables has a non-canonical address (a memory operand addressed through SS).
#GP(0)An element that the mask enables has an effective address that its segment (CS, DS, ES, FS or GS) does not allow, such as one beyond the limit.
#GP(0)An element that the mask enables has a non-canonical address.
#GP(0)An element that the mask enables extends past offset FFFFh of its segment.
#PF(fault-code)Accessing an element that the mask enables causes a page fault.
#AC(0)Code at privilege level 3 makes a misaligned 2-, 4- or 8-byte memory access while alignment checking is on.

Notes

The memory operand may have any alignment, and memory faults come only from the elements that the mask enables. The class has #AC but no #XM.

The manual marks many of these instructions E4.nb: they have no embedded broadcast, so EVEX.b with a memory operand raises #UD. Among them are the unaligned moves VMOVUPS, VMOVUPD and VMOVDQU8 to VMOVDQU64, the compress and expand instructions, and most instructions on bytes and words (Table 2-45).

XED also puts here the EVEX forms of VAESENC, VAESENCLAST, VAESDEC, VAESDECLAST, VGF2P8AFFINEQB, VGF2P8AFFINEINVQB and VPCLMULQDQ, and VCVTNE2PS2BF16, VP2INTERSECTD and VP2INTERSECTQ, which the manual’s pages refer to Type E4NF, without fault suppression or #AC (AVX512-E4NF).

The AVX10.2 specification lists its BF16 arithmetic and new dot products here, such as VADDBF16 and VPDPBSSD, and repeats the table with #GP(0) in protected mode for an enabled element addressed through DS, ES, FS or GS while that register holds a null selector. It lists VCVTHF82PH under Type E2, which XED puts here.

  • avx-type-4: VEX-encoded integer, logical, shuffle and cryptographic instructions without floating-point exceptions, such as VPADDD, VPSHUFB and VAESENC, which Intel's manual calls Exceptions Type 4.
  • AVX512-E4NF: EVEX-encoded permutes, shuffles and other instructions without floating-point exceptions or fault suppression, such as VPERMD, VSHUFPS and VPUNPCKLDQ, which Intel's manual calls Exceptions Type E4NF.
  • AVX512-E2: EVEX-encoded floating-point arithmetic on full vectors, such as VADDPS, VFMADD231PD and VCVTPS2DQ, with memory fault suppression, which Intel's manual calls Exceptions Type E2.

Instructions

Intel XED puts forms of 254 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX10.1

AVX10.2

AVX10_V2_AUX

AVX512_4VNNIW

AVX512-VP2INTERSECT

MOVRS

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.4, Table 2-51; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapters 3 to 5, the pages of the instructions named in the notes.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 15.6.1.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026): Section 4.1 and Table 4.6.
  4. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.