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AVX-512

AVX512-E4NF exception class

EVEX-encoded permutes, shuffles and other instructions without floating-point exceptions or fault suppression, such as VPERMD, VSHUFPS and VPUNPCKLDQ, which Intel's manual calls Exceptions Type E4NF.

Class
AVX512-E4NF in Intel XED
Applies to
EVEX encodings, 128 to 512 bits.
Instructions
86 mnemonics, 520 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no EVEX prefix.
#UDThe operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7).
#UDAn EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the EVEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.

Notes

Without fault suppression, a fault on any element of the memory operand counts, whatever the mask. Unlike AVX512-E4, the class has no #AC.

The manual marks some of these instructions E4NF.nb: they have no embedded broadcast, so EVEX.b with a memory operand raises #UD, such as VPSHUFB, VPALIGNR and the byte and word unpacks (Table 2-45).

The AVX10.2 specification lists its FP8 conversions, such as VCVTPH2BF8, and the EVEX form of VMPSADBW here. Its version of the table has two more rows: #AC(0) for a misaligned access under alignment checking at privilege level 3, and #GP(0) in protected mode for a memory operand addressed through DS, ES, FS or GS while that register holds a null selector.

  • AVX512-E4: EVEX-encoded integer, logical and other instructions without floating-point exceptions, such as VPADDD, VPTERNLOGD and VMOVDQU32, with memory fault suppression, which Intel's manual calls Exceptions Type E4.
  • avx-type-4: VEX-encoded integer, logical, shuffle and cryptographic instructions without floating-point exceptions, such as VPADDD, VPSHUFB and VAESENC, which Intel's manual calls Exceptions Type 4.
  • avx-type-6: VEX-encoded instructions without a legacy SSE form, such as VBROADCASTSS, VINSERTF128, VPERM2I128 and VMASKMOVPS, which Intel's manual calls Exceptions Type 6.

Instructions

Intel XED puts forms of 86 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX10.1

AVX10.2

AVX10_V2_AUX

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.4, Table 2-52; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43.
  2. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026): Section 4.1 and Table 4.7.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.