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AVX-512

AVX512-E5 exception class

EVEX-encoded instructions that read part of a vector or a scalar from memory, such as VPMOVZXBD and VCVTDQ2PD, with memory fault suppression, which Intel's manual calls Exceptions Type E5.

Class
AVX512-E5 in Intel XED
Applies to
EVEX encodings, 128 to 512 bits.
Instructions
17 mnemonics, 93 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no EVEX prefix.
#UDThe operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7).
#UDAn EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the EVEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)An element that the mask enables lies outside the stack segment (a memory operand addressed through SS).
#SS(0)An element that the mask enables has a non-canonical address (a memory operand addressed through SS).
#GP(0)An element that the mask enables has an effective address that its segment (CS, DS, ES, FS or GS) does not allow, such as one beyond the limit.
#GP(0)An element that the mask enables has a non-canonical address.
#GP(0)An element that the mask enables extends past offset FFFFh of its segment.
#PF(fault-code)Accessing an element that the mask enables causes a page fault.
#AC(0)Code at privilege level 3 makes a misaligned 2-, 4- or 8-byte memory access while alignment checking is on.

Notes

The memory operand may have any alignment, and memory faults come only from the elements that the mask enables. The class has no #XM. The pages of VPMOVSX and VPMOVZX add #UD for an EVEX.vvvv other than 1111b.

XED also puts the EVEX forms of VMOVSS and VMOVSD here, which the manual’s pages and Table 2-45 list under Type E10 (AVX512-E10).

  • avx-type-5: VEX-encoded moves, inserts, extracts and conversions on operands smaller than 16 bytes without floating-point exceptions, such as VMOVD, VPINSRB and VPMOVZXBW, which Intel's manual calls Exceptions Type 5.
  • AVX512-E5NF: The EVEX-encoded VMOVDDUP, which duplicates double-precision elements, without fault suppression, the one instruction of what Intel's manual calls Exceptions Type E5NF.
  • AVX512-E10: EVEX-encoded scalar instructions that ignore the vector length, such as VRCP14SS and VFPCLASSSH, with memory fault suppression, which Intel's manual calls Exceptions Type E10.

Instructions

Intel XED puts forms of 17 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX10.1

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.5, Table 2-53; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapter 4, MOVSD, MOVSS, PMOVSX and PMOVZX.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 15.6.1.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.