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AVX-512

AVX512-E6 exception class

EVEX-encoded broadcasts and down-converting stores, such as VBROADCASTSS and VPMOVDB, with memory fault suppression, which Intel's manual calls Exceptions Type E6.

Class
AVX512-E6 in Intel XED
Applies to
EVEX encodings, 128 to 512 bits.
Instructions
37 mnemonics, 125 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no EVEX prefix.
#UDThe operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7).
#UDAn EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the EVEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)An element that the mask enables lies outside the stack segment (a memory operand addressed through SS).
#SS(0)An element that the mask enables has a non-canonical address (a memory operand addressed through SS).
#GP(0)An element that the mask enables has an effective address that its segment (CS, DS, ES, FS or GS) does not allow, such as one beyond the limit.
#GP(0)An element that the mask enables has a non-canonical address.
#PF(fault-code)Accessing an element that the mask enables causes a page fault.
#AC(0)Code at privilege level 3 makes a misaligned 2-, 4- or 8-byte memory access while alignment checking is on.

Notes

The manual’s table lists these conditions for protected and 64-bit mode only. Memory faults come only from the elements that the mask enables.

XED puts here the forms of the down-converting moves VPMOVDB to VPMOVUSWB that store to memory, and their forms with a register destination in AVX512-E6NF; the manual’s pages refer both to Type E6 and add #UD for an EVEX.vvvv other than 1111b. The broadcasts from a general-purpose register are AVX512-E7NM. The manual also lists VFPCLASSSD and VFPCLASSSS here, which XED puts in AVX512-E10.

  • avx-type-6: VEX-encoded instructions without a legacy SSE form, such as VBROADCASTSS, VINSERTF128, VPERM2I128 and VMASKMOVPS, which Intel's manual calls Exceptions Type 6.
  • AVX512-E6NF: EVEX-encoded extracts and inserts of 128- and 256-bit lanes, such as VEXTRACTF32X4 and VINSERTI64X4, without fault suppression, which Intel's manual calls Exceptions Type E6NF.
  • AVX512-E7NM: EVEX-encoded instructions without a memory operand, such as VPMOVM2D, VPMOVD2M and the broadcasts from a general-purpose register, which Intel's manual calls Exceptions Type E7NM.

Instructions

Intel XED puts forms of 37 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX10.1

AVX10_V2_AUX

SM4

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.6, Table 2-55; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapter 5, VPMOVDB and the other down-converting moves.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Section 15.6.1.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.