AVX-512
AVX512-E6NF exception class
EVEX-encoded extracts and inserts of 128- and 256-bit lanes, such as VEXTRACTF32X4 and VINSERTI64X4, without fault suppression, which Intel's manual calls Exceptions Type E6NF.
- Class
AVX512-E6NFin Intel XED- Applies to
- EVEX encodings, 128 to 512 bits.
- Instructions
- 37 mnemonics, 111 forms
- Data
- Intel XED v2026.08.23
Exception conditions
| Exception | Real | Virtual-8086 | Protected | 64-bit | Condition |
|---|---|---|---|---|---|
#UD | yes | yes | no | no | Always: real and virtual-8086 mode have no EVEX prefix. |
#UD | no | no | yes | yes | The operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7). |
#UD | no | no | yes | yes | An EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks. |
#UD | no | no | yes | yes | The instruction has a LOCK prefix (F0). |
#UD | no | no | yes | yes | A REX, F2, F3 or 66 prefix comes before the EVEX prefix. |
#UD | no | no | yes | yes | The processor lacks the instruction’s extension: its CPUID feature flag is 0. |
#NM | no | no | yes | yes | CR0.TS (task switched, bit 3) is 1. |
#SS(0) | no | no | yes | no | A memory operand addressed through SS lies outside the stack segment. |
#SS(0) | no | no | no | yes | A memory operand addressed through SS has a non-canonical address. |
#GP(0) | no | no | yes | no | A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit. |
#GP(0) | no | no | no | yes | A memory operand has a non-canonical address. |
#PF(fault-code) | no | no | yes | yes | Accessing a memory operand causes a page fault. |
#AC(0) | no | no | yes | yes | Code at privilege level 3 makes a misaligned 2-, 4- or 8-byte memory access while alignment checking is on. |
Notes
Besides the extracts and inserts, the class holds VPBROADCASTMB2Q and VPBROADCASTMW2D, which broadcast a mask register. Without fault suppression, a fault on any element of the memory operand counts, whatever the mask. The pages of the extracts add #UD for an EVEX.vvvv other than 1111b.
XED also puts here the forms of the down-converting moves VPMOVDB to VPMOVUSWB with a register destination, which the manual’s pages refer to Type E6 (AVX512-E6).
Related classes
Instructions
Intel XED puts forms of 37 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.
AVX10.1
- VEXTRACTF32X4
- VEXTRACTF32X8
- VEXTRACTF64X2
- VEXTRACTF64X4
- VEXTRACTI32X4
- VEXTRACTI32X8
- VEXTRACTI64X2
- VEXTRACTI64X4
- VINSERTF32X4
- VINSERTF32X8
- VINSERTF64X2
- VINSERTF64X4
- VINSERTI32X4
- VINSERTI32X8
- VINSERTI64X2
- VINSERTI64X4
- VPBROADCASTMB2Q
- VPBROADCASTMW2D
- VPMOVDB
- VPMOVDW
- VPMOVQB
- VPMOVQD
- VPMOVQW
- VPMOVSDB
- VPMOVSDW
- VPMOVSQB
- VPMOVSQD
- VPMOVSQW
- VPMOVSWB
- VPMOVUSDB
- VPMOVUSDW
- VPMOVUSQB
- VPMOVUSQD
- VPMOVUSQW
- VPMOVUSWB
- VPMOVWB
AVX10_V2_AUX
Sources
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.6, Table 2-56; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapter 5, VEXTRACTF128, VINSERTF128, VPBROADCASTM and VPMOVDB.
- Intel XED v2026.08.23 (commit
0bcb6237345c): the exception class of each instruction form.
The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.