Class
AVX512-E7NM in Intel XED
Applies to
EVEX encodings that use registers only.
Instructions
16 mnemonics, 48 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDyesyesnonoAlways: real and virtual-8086 mode have no EVEX prefix.
#UDnonoyesyesThe operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7).
#UDnonoyesyesAn EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks.
#UDyesyesyesyesThe instruction has a LOCK prefix (F0).
#UDnonoyesyesA REX, F2, F3 or 66 prefix comes before the EVEX prefix.
#UDyesyesyesyesThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMnonoyesyesCR0.TS (task switched, bit 3) is 1.

Notes

Without a memory operand, only #UD and #NM remain; the table marks #NM for protected and 64-bit mode only. VPBROADCASTB, VPBROADCASTW, VPBROADCASTD and VPBROADCASTQ are here with a general-purpose register as their source, and in AVX512-E6 with a vector register or memory. The pages of VPMOVM2B, VPMOVB2M and their relatives add #UD for an EVEX.vvvv other than 1111b.

Instructions

Intel XED puts forms of 16 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX10.1

AVX10_V2_AUX

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.7, Table 2-57; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapter 5, VPMOVM2B and VPMOVB2M.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.