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AVX-512

AVX512-E7NM128 exception class

The EVEX-encoded VMOVHLPS and VMOVLHPS, register moves that exist only as 128-bit forms, which Intel's manual calls Exceptions Type E7NM.128.

Class
AVX512-E7NM128 in Intel XED
Applies to
The EVEX encodings of VMOVHLPS and VMOVLHPS.
Instructions
2 mnemonics, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: real and virtual-8086 mode have no EVEX prefix.
#UDThe operating system has not enabled the state the instruction uses: CR4.OSXSAVE is 0, or XCR0 lacks one of the bits Table 2-39 requires (for EVEX, bits 1 and 2 and the opmask and ZMM bits 5 to 7).
#UDAn EVEX field has a value that the manual’s general rules forbid: a bit with a fixed value or the opcode map (Table 2-40), a register field (Table 2-41), the opmask and zeroing fields (Table 2-42), EVEX.b where the instruction gives it no meaning (Table 2-43), or a vector length (EVEX.L’L) that the instruction lacks.
#UDEVEX.L'L is not 00b: the instructions exist only as 128-bit forms.
#UDThe instruction has a LOCK prefix (F0).
#UDA REX, F2, F3 or 66 prefix comes before the EVEX prefix.
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.

Notes

Table 2-45 marks VMOVHLPS and VMOVLHPS as E7NM.128: the conditions of AVX512-E7NM, and #UD for any vector length but 128 bits. Their VEX forms are avx-type-7.

  • AVX512-E7NM: EVEX-encoded instructions without a memory operand, such as VPMOVM2D, VPMOVD2M and the broadcasts from a general-purpose register, which Intel's manual calls Exceptions Type E7NM.
  • avx-type-7: VEX-encoded instructions without a memory operand or floating-point exceptions, such as VMOVMSKPS, VPSRLDQ and the shifts by an immediate count, which Intel's manual calls Exceptions Type 7.

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

AVX10.1

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.8.7, Table 2-57; Section 2.8, Tables 2-44 and 2-45; Section 2.7.11, Tables 2-39 to 2-43; Chapter 4, MOVHLPS and MOVLHPS.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.