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Other legacy-encoded instructions

LEGACY-MOVRS exception class

LEGACY-MOVRS is the ISE's exception class Legacy-MOVRS of the MOVRS load in its legacy encoding: #UD outside 64-bit mode or with a LOCK or REP prefix, and the faults of an ordinary load.

Class
LEGACY-MOVRS in Intel XED
Applies to
The legacy encodings of MOVRS (MOVRS), 0F 38 8A and 8B with a memory source.
Instructions
1 mnemonic, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: MOVRS exists only in 64-bit mode.
#UDA LOCK prefix or a REP prefix (F2H or F3H) is used.
#UDCPUID reports no MOVRS.
#SS(0)The memory address uses the SS segment and is not canonical.
#GP(0)The memory address is not canonical.
#PF(fault-code)The load causes a page fault.
#AC(0)Alignment checking is enabled, CPL is 3 and the load is unaligned.

Notes

MOVRS loads like MOV but tells the processor that other processors are likely to read the data before anyone writes it, so the caches can keep it ready for sharing. Its exceptions are those of an ordinary load plus the mode and prefix checks. The EVEX vector forms (VMOVRSB, VMOVRSW, VMOVRSD and VMOVRSQ) have the AVX-512 class E4 instead, and the APX encoding of MOVRS has APX-EVEX-MOVRS.

  • APX-EVEX-MOVRS: APX-EVEX-MOVRS is the APX specification's exception class for MOVRS in its EVEX encoding, a load with a hint that other processors will read the same data.
  • LEGACY-PREFETCH: LEGACY-PREFETCH is XED's name for the exceptions of PREFETCHRST2, which the ISE lists on the instruction's page: #UD for a LOCK prefix, in every mode, and nothing else.
  • AVX512-E4: EVEX-encoded integer, logical and other instructions without floating-point exceptions, such as VPADDD, VPTERNLOGD and VMOVDQU32, with memory fault suppression, which Intel's manual calls Exceptions Type E4.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

MOVRS

Sources

  1. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): MOVRS, Description and Exceptions; Table 2-1.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.