Class
LEGACY-PREFETCH in Intel XED
Applies to
PREFETCHRST2 (MOVRS), 0F 18 /4 with a memory operand.
Instructions
1 mnemonic, 1 form
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDyesyesyesyesA LOCK prefix is used.

Notes

No Intel document defines this class; its single row is the exception section of PREFETCHRST2 in the ISE. The instruction fetches the line that holds its byte operand toward the processor, preferring a place that suits data other processors will also read. It is a hint that does not change what the program computes, so its memory operand raises no fault.

Unlike MOVRS, PREFETCHRST2 works in every mode, and the ISE names no CPUID condition for it.

Instructions

Intel XED puts forms of 1 mnemonic in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

MOVRS

Sources

  1. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): PREFETCHRST2, Description and Exceptions.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.