Other legacy-encoded instructions
LEGACY-RAO-INT exception class
LEGACY-RAO-INT is XED's name for the exceptions of the remote atomic operations AADD, AAND, AOR and AXOR in their legacy encoding, which the ISE lists on the instruction pages rather than as a named class.
- Class
LEGACY-RAO-INTin Intel XED- Applies to
- The legacy encodings of AADD, AAND, AOR and AXOR (RAO-INT): NP, 66, F2 and F3 0F 38 FC with a memory destination.
- Instructions
- 4 mnemonics, 8 forms
- Data
- Intel XED v2026.08.23
Exception conditions
| Exception | Real | Virtual-8086 | Protected | 64-bit | Condition |
|---|---|---|---|---|---|
#UD | yes | yes | yes | yes | A LOCK prefix is used. |
#UD | yes | yes | yes | yes | CPUID reports no RAO-INT (CPUID.(EAX=07H,ECX=1):EAX bit 3). |
#SS | yes | no | no | no | The memory address is not valid in the SS segment. |
#SS(0) | no | yes | yes | no | The memory address is not valid in the SS segment. |
#SS(0) | no | no | no | yes | The memory address uses the SS segment and is not canonical. |
#GP | yes | no | no | no | The operand reaches past offset FFFFH of its segment. |
#GP(0) | no | yes | yes | no | The memory address is not valid in the CS, DS, ES, FS or GS segment it uses. |
#GP(0) | no | no | no | yes | The memory address is not canonical. |
#GP | yes | no | no | no | The destination is not 4-byte aligned. |
#GP | yes | no | no | no | The destination’s memory type is not write-back (WB). |
#GP(0) | no | yes | yes | no | The destination is not 4-byte aligned. |
#GP(0) | no | no | no | yes | The destination is not naturally aligned: to 4 bytes, or to 8 for the 64-bit form. |
#GP(0) | no | yes | yes | yes | The destination’s memory type is not write-back (WB). |
#PF(fault-code) | no | yes | yes | yes | The memory access causes a page fault. |
Notes
No Intel document defines this class. The rows come from the exception sections of AADD, AAND, AOR and AXOR in the ISE, which are the same for all four. The instructions work in every mode; only their 64-bit forms, with REX.W, need 64-bit mode.
Remote atomic operations may be carried out close to memory, in a shared cache or the memory controller. They require natural alignment so that one update never straddles two cache lines, and a misaligned destination, like one whose memory type is not write-back, raises #GP rather than #AC. They are atomic without a LOCK prefix, which raises #UD.
Related classes
Instructions
Intel XED puts forms of 4 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.
RAO-INT
Sources
- Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): AADD, AAND, AOR and AXOR, Description and Exceptions; Sections 5.1 and 5.3.
- Intel XED v2026.08.23 (commit
0bcb6237345c): the exception class of each instruction form.
The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.