Class
LEGACY-RAO-INT in Intel XED
Applies to
The legacy encodings of AADD, AAND, AOR and AXOR (RAO-INT): NP, 66, F2 and F3 0F 38 FC with a memory destination.
Instructions
4 mnemonics, 8 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDyesyesyesyesA LOCK prefix is used.
#UDyesyesyesyesCPUID reports no RAO-INT (CPUID.(EAX=07H,ECX=1):EAX bit 3).
#SSyesnononoThe memory address is not valid in the SS segment.
#SS(0)noyesyesnoThe memory address is not valid in the SS segment.
#SS(0)nononoyesThe memory address uses the SS segment and is not canonical.
#GPyesnononoThe operand reaches past offset FFFFH of its segment.
#GP(0)noyesyesnoThe memory address is not valid in the CS, DS, ES, FS or GS segment it uses.
#GP(0)nononoyesThe memory address is not canonical.
#GPyesnononoThe destination is not 4-byte aligned.
#GPyesnononoThe destination’s memory type is not write-back (WB).
#GP(0)noyesyesnoThe destination is not 4-byte aligned.
#GP(0)nononoyesThe destination is not naturally aligned: to 4 bytes, or to 8 for the 64-bit form.
#GP(0)noyesyesyesThe destination’s memory type is not write-back (WB).
#PF(fault-code)noyesyesyesThe memory access causes a page fault.

Notes

No Intel document defines this class. The rows come from the exception sections of AADD, AAND, AOR and AXOR in the ISE, which are the same for all four. The instructions work in every mode; only their 64-bit forms, with REX.W, need 64-bit mode.

Remote atomic operations may be carried out close to memory, in a shared cache or the memory controller. They require natural alignment so that one update never straddles two cache lines, and a misaligned destination, like one whose memory type is not write-back, raises #GP rather than #AC. They are atomic without a LOCK prefix, which raises #UD.

Instructions

Intel XED puts forms of 4 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

RAO-INT

Sources

  1. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026): AADD, AAND, AOR and AXOR, Description and Exceptions; Sections 5.1 and 5.3.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.