x86-64.net

MMX

mmx-fp exception class

The SSE conversions CVTPI2PS, CVTPS2PI and CVTTPS2PI between MMX and XMM registers, which can raise SIMD floating-point exceptions, as Intel's manual lists them among the legacy SIMD/MMX instructions with XMM and FP exception.

Class
mmx-fp in Intel XED
Applies to
The legacy forms of CVTPI2PS, CVTPS2PI and CVTTPS2PI.
Instructions
3 mnemonics, 6 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDA SIMD floating-point exception that MXCSR does not mask occurs while CR4.OSXMMEXCPT is 0, the setting for an operating system that does not handle #XM.
#UDCR0.EM is 1, or CR4.OSFXSR is 0: the operating system has not enabled SSE.
#UDThe instruction has a LOCK prefix (F0).
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#MFAn unmasked x87 floating-point exception from an earlier x87 instruction is still pending.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.
#AC(0)Code at privilege level 3 accesses a misaligned memory operand while alignment checking is on.
#XMA SIMD floating-point exception that MXCSR does not mask occurs, and CR4.OSXMMEXCPT is 1.

Notes

These instructions follow both sets of rules: as SSE instructions they need CR4.OSFXSR and raise #XM (or #UD) for SIMD floating-point exceptions, and as instructions on MMX registers they raise #MF for a pending x87 exception. The 8-byte memory operand needs no alignment unless alignment checking is on.

  • mmx-fp-16align: The SSE2 conversions CVTPD2PI and CVTTPD2PI from double precision to integers in an MMX register, which need an aligned 16-byte memory operand, as Intel's manual lists them among the legacy SIMD/MMX instructions with FP exception and 16-byte alignment.
  • mmx-nofp: CVTPI2PD, which converts two integers from an MMX register or memory to double precision without floating-point exceptions, as Intel's manual lists it among the legacy SIMD/MMX instructions with XMM and without FP exception.
  • SSE_TYPE_3: Legacy SSE floating-point arithmetic on scalars and other operands smaller than 16 bytes, such as ADDSS, COMISD and CVTSI2SD, which Intel's manual calls Exceptions Type 3.

Instructions

Intel XED puts forms of 3 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

SSE

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Section 25.25.3, Table 25-5.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5, the note on instructions that operate on MMX registers.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.