x86-64.net

MMX

mmx-mem exception class

MMX instructions on MMX registers and 8-byte memory operands, such as PADDB, PMADDWD and PSHUFW, which Intel's manual lists as SIMD/MMX instructions with a memory reference.

Class
mmx-mem in Intel XED
Applies to
Legacy encodings on MMX registers, including the SSE, SSE2 and SSSE3 instructions that use them, such as PAVGB, PADDQ and PSHUFB.
Instructions
71 mnemonics, 133 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDCR0.EM is 1: the operating system emulates the x87 FPU, which the MMX registers share.
#UDThe instruction has a LOCK prefix (F0).
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#MFAn unmasked x87 floating-point exception from an earlier x87 instruction is still pending.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.
#AC(0)Code at privilege level 3 accesses a misaligned memory operand while alignment checking is on.

Notes

The MMX registers are the x87 registers under another name, so these instructions follow x87 rules: they raise #UD when CR0.EM is 1, with no condition on CR4.OSFXSR in the manual’s table, and #MF when an unmasked x87 exception is still pending from an earlier x87 instruction; the instruction runs once the handler returns. They raise no SIMD floating-point exceptions.

XED gives the class to most, but not all, of the forms that the manual’s table covers: both forms of PUNPCKLDQ and the register forms of several others, such as PAND, PCMPGTB and PMULHW, have no class in XED. MOVD and POR, which none of the section’s tables lists, have none either.

  • mmx-nomem: PEXTRW and PMOVMSKB with MMX registers, which have no memory operand, as Intel's manual lists them among the SIMD/MMX instructions without a memory reference.
  • mmx-nofp2: The MMX moves MOVQ, MOVNTQ and MASKMOVQ, which raise no floating-point exceptions, as Intel's manual lists them among the legacy SIMD/MMX instructions without FP exception.
  • SSE_TYPE_4: Legacy SSE instructions with a 16-byte memory operand and no floating-point exceptions, such as PADDD, PSHUFB, ANDPS and AESENC, which Intel's manual calls Exceptions Type 4.

Instructions

Intel XED puts forms of 71 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

MMX

SSE

SSE2

SSSE3

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Section 25.25.3, Table 25-7.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5, the note on instructions that operate on MMX registers.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026): Sections 9.2.2 and 9.6.7.
  4. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.