MMX
mmx-nofp2 exception class
The MMX moves MOVQ, MOVNTQ and MASKMOVQ, which raise no floating-point exceptions, as Intel's manual lists them among the legacy SIMD/MMX instructions without FP exception.
- Class
mmx-nofp2in Intel XED- Applies to
- The legacy forms of MOVQ, MOVNTQ and MASKMOVQ that use MMX registers.
- Instructions
- 3 mnemonics, 10 forms
- Data
- Intel XED v2026.08.23
Exception conditions
| Exception | Real | Virtual-8086 | Protected | 64-bit | Condition |
|---|---|---|---|---|---|
#UD | yes | yes | yes | yes | CR0.EM is 1: the operating system emulates the x87 FPU, which the MMX registers share. |
#UD | yes | yes | yes | yes | MASKMOVQ has a memory operand in its ModR/M byte (mod is not 11b): it takes two registers and stores through DS:rDI. |
#UD | yes | yes | yes | yes | The instruction has a LOCK prefix (F0). |
#UD | yes | yes | yes | yes | The processor lacks the instruction’s extension: its CPUID feature flag is 0. |
#MF | yes | yes | yes | yes | An unmasked x87 floating-point exception from an earlier x87 instruction is still pending. |
#NM | yes | yes | yes | yes | CR0.TS (task switched, bit 3) is 1. |
#SS(0) | no | no | yes | no | A memory operand addressed through SS lies outside the stack segment. |
#SS(0) | no | no | no | yes | A memory operand addressed through SS has a non-canonical address. |
#GP(0) | no | no | yes | no | A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit. |
#GP(0) | no | no | yes | no | MASKMOVQ, or a MOVQ that stores an MMX register, writes to a segment that cannot be written. |
#GP(0) | no | no | yes | no | MASKMOVQ stores through DS, ES, FS or GS while that register holds a null selector. |
#GP(0) | no | no | no | yes | A memory operand has a non-canonical address. |
#GP(0) | yes | yes | no | no | A memory operand extends past offset FFFFh of its segment. |
#PF(fault-code) | no | yes | yes | yes | Accessing a memory operand causes a page fault. |
#AC(0) | no | yes | yes | yes | Code at privilege level 3 accesses a misaligned memory operand while alignment checking is on. |
Notes
The rows for a memory operand in the ModR/M byte and for a null selector apply to MASKMOVQ only, and the one for a segment that cannot be written to MASKMOVQ and MOVQ, as notes to the manual’s table say.
Related classes
Instructions
Intel XED puts forms of 3 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.
MMX
SSE
Sources
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Section 25.25.3, Table 25-8.
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5, the note on instructions that operate on MMX registers.
- Intel XED v2026.08.23 (commit
0bcb6237345c): the exception class of each instruction form.
The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.