x86-64.net

MMX

mmx-nomem exception class

PEXTRW and PMOVMSKB with MMX registers, which have no memory operand, as Intel's manual lists them among the SIMD/MMX instructions without a memory reference.

Class
mmx-nomem in Intel XED
Applies to
The legacy forms of PEXTRW and PMOVMSKB that read an MMX register.
Instructions
2 mnemonics, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDCR0.EM is 1: the operating system emulates the x87 FPU, which the MMX registers share.
#UDThe instruction has a LOCK prefix (F0).
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#MFAn unmasked x87 floating-point exception from an earlier x87 instruction is still pending.
#NMCR0.TS (task switched, bit 3) is 1.

Notes

Without a memory operand, only #UD, #MF and #NM remain. The manual’s table marks #NM for protected and 64-bit mode only.

  • mmx-mem: MMX instructions on MMX registers and 8-byte memory operands, such as PADDB, PMADDWD and PSHUFW, which Intel's manual lists as SIMD/MMX instructions with a memory reference.
  • SSE_TYPE_7: Legacy SSE instructions without a memory operand or floating-point exceptions, such as MOVMSKPS, PSLLDQ and the shifts by an immediate count, which Intel's manual calls Exceptions Type 7.

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

SSE

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Section 25.25.3, Table 25-9.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5, the note on instructions that operate on MMX registers.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.