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MSR instructions

MSR-IMM-EVEX exception class

MSR-IMM-EVEX is the APX specification's exception class for RDMSR and WRMSRNS with an immediate MSR address in their EVEX encoding, which lets the register operand be R16 to R31.

Class
MSR-IMM-EVEX in Intel XED
Applies to
The EVEX encodings (map 7) of RDMSR r64, imm32 and WRMSRNS imm32, r64 (MSR_IMM with APX).
Instructions
2 mnemonics, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the immediate forms exist only in 64-bit mode.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDEVEX.L is 1, or EVEX.V4 and EVEX.vvvv are not all 1s.
#UDA bit of the last EVEX payload byte other than V4 is 1.
#UDCPUID reports no MSR_IMM or no APX_F.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#GP(0)CPL is not 0.
#GP(0)RDMSR, WRMSR or WRMSRNS of the same MSR would raise #GP(0), for example for an MSR that does not exist or for reserved bits in the value.

Notes

The APX table says that any set bit of the last EVEX payload byte raises #UD, but that byte also holds V4, which the table’s previous row requires to be 1. The entry follows the tables of the other APX classes, which exempt V4. The EVEX encoding lets the register operand be one of R16 to R31.

  • MSR-IMM-VEX: MSR-IMM-VEX is XED's name for the exceptions of the VEX-encoded forms of RDMSR and WRMSRNS that take the MSR address as an immediate, which Intel documents on the instruction pages rather than as a named class.
  • USER-MSR-EVEX: USER-MSR-EVEX is the APX specification's exception class for URDMSR and UWRMSR in their EVEX encoding, with the MSR address in a register or an immediate and the registers R16 to R31 available.

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.21, Table 4.22.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.