x86-64.net

MSR instructions

MSR-IMM-VEX exception class

MSR-IMM-VEX is XED's name for the exceptions of the VEX-encoded forms of RDMSR and WRMSRNS that take the MSR address as an immediate, which Intel documents on the instruction pages rather than as a named class.

Class
MSR-IMM-VEX in Intel XED
Applies to
The VEX encodings (map 7) of RDMSR r64, imm32 and WRMSRNS imm32, r64 (MSR_IMM).
Instructions
2 mnemonics, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: the immediate forms exist only in 64-bit mode.
#UDA LOCK prefix is used.
#UDCPUID reports no MSR_IMM (CPUID.(EAX=07H,ECX=1):ECX bit 5).
#GP(0)CPL is not 0.
#GP(0)The MSR address in the immediate is reserved or not implemented.
#GP(0)WRMSRNS only: the value sets reserved bits of the MSR.
#GP(0)WRMSRNS only: the value is a non-canonical address and the MSR holds an address, such as IA32_LSTAR, IA32_FS_BASE or IA32_GS_BASE.

Notes

No Intel document defines this class. The rows come from the exception sections of RDMSR and WRMSRNS in SDM Volume 2, which describe the implicit ECX forms and the immediate forms together; the SDM names no #UD conditions for the VEX fields of the immediate forms, unlike the APX table of their EVEX forms (MSR-IMM-EVEX). With the MSR address in the instruction, the SDM notes that the immediate form may perform better than the ECX form, and RDMSR then writes one 64-bit register instead of EDX:EAX.

  • MSR-IMM-EVEX: MSR-IMM-EVEX is the APX specification's exception class for RDMSR and WRMSRNS with an immediate MSR address in their EVEX encoding, which lets the register operand be R16 to R31.
  • USER-MSR-VEX: USER-MSR-VEX is XED's name for the exceptions of the VEX-encoded URDMSR and UWRMSR with an immediate MSR address, which Intel documents on the instruction pages rather than as a named class.

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

MSR_IMM

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): RDMSR and WRMSRNS, Description and Exceptions.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.