SSE_TYPE_1 exception class

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.

Exception	Real	Virtual-8086	Protected	64-bit	Condition
`#UD`	yes	yes	yes	yes	The operating system has not enabled SSE: `CR0.EM` is 1 or `CR4.OSFXSR` is 0.
`#UD`	yes	yes	yes	yes	The instruction has a LOCK prefix (F0).
`#UD`	yes	yes	yes	yes	The processor lacks the instruction’s extension: its CPUID feature flag is 0.
`#NM`	yes	yes	yes	yes	`CR0.TS` (task switched, bit 3) is 1.
`#SS(0)`	no	no	yes	no	A memory operand addressed through SS lies outside the stack segment.
`#SS(0)`	no	no	no	yes	A memory operand addressed through SS has a non-canonical address.
`#GP(0)`	yes	yes	yes	yes	A 16-byte memory operand starts at an address that is not a multiple of 16.
`#GP(0)`	no	no	yes	no	A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
`#GP(0)`	no	no	no	yes	A memory operand has a non-canonical address.
`#GP(0)`	yes	yes	no	no	A memory operand extends past offset FFFFh of its segment.
`#PF(fault-code)`	no	yes	yes	yes	Accessing a memory operand causes a page fault.

Notes

Alignment is the rule of this class: every memory operand must sit on a 16-byte boundary, in every processor mode, or the instruction raises #GP(0). Alignment checking plays no part, and the class has no #AC.

The instructions only move data, so there are no SIMD floating-point exceptions. MOVUPS, MOVUPD and MOVDQU make the same moves without the alignment rule (SSE_TYPE_4M).

Instructions

Intel XED puts forms of 7 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

SSE

SSE2

SSE4.1

MOVNTDQA

Exception conditions

Notes

Related classes

Instructions

SSE

SSE2

SSE4.1

Sources