Class
SSE_TYPE_2D in Intel XED
Applies to
Legacy encodings of DPPD and DPPS.
Instructions
2 mnemonics, 4 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDyesyesyesyesA SIMD floating-point exception that MXCSR does not mask occurs while CR4.OSXMMEXCPT is 0, the setting for an operating system that does not handle #XM.
#UDyesyesyesyesThe operating system has not enabled SSE: CR0.EM is 1 or CR4.OSFXSR is 0.
#UDyesyesyesyesThe instruction has a LOCK prefix (F0).
#UDyesyesyesyesThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMyesyesyesyesCR0.TS (task switched, bit 3) is 1.
#SS(0)nonoyesnoA memory operand addressed through SS lies outside the stack segment.
#SS(0)nononoyesA memory operand addressed through SS has a non-canonical address.
#GP(0)yesyesyesyesA 16-byte memory operand starts at an address that is not a multiple of 16.
#GP(0)nonoyesnoA memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)nononoyesA memory operand has a non-canonical address.
#GP(0)yesyesnonoA memory operand extends past offset FFFFh of its segment.
#PF(fault-code)noyesyesyesAccessing a memory operand causes a page fault.
#XMyesyesyesyesA SIMD floating-point exception that MXCSR does not mask occurs, and CR4.OSXMMEXCPT is 1.

Notes

XED gives the two dot products a class of their own. The manual’s pages for DPPD and DPPS refer the legacy forms to the Type 2 table without adding anything, so the conditions are those of SSE_TYPE_2. The one extra condition, #UD for VEX.L = 1, concerns VDPPD (avx-type-2D).

A dot product checks each of its multiplications and additions for floating-point exceptions in turn. When one raises an unmasked exception, the destination keeps its old value.

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

SSE4.1

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.2, Table 2-19; Section 2.5, Table 2-15; Chapter 3, DPPD and DPPS.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.