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SSE

SSE_TYPE_3 exception class

Legacy SSE floating-point arithmetic on scalars and other operands smaller than 16 bytes, such as ADDSS, COMISD and CVTSI2SD, which Intel's manual calls Exceptions Type 3.

Class
SSE_TYPE_3 in Intel XED
Applies to
Legacy SSE encodings, without a VEX or EVEX prefix.
Instructions
31 mnemonics, 74 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDA SIMD floating-point exception that MXCSR does not mask occurs while CR4.OSXMMEXCPT is 0, the setting for an operating system that does not handle #XM.
#UDThe operating system has not enabled SSE: CR0.EM is 1 or CR4.OSFXSR is 0.
#UDThe instruction has a LOCK prefix (F0).
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.
#AC(0)Code at privilege level 3 makes a misaligned 2-, 4- or 8-byte memory access while alignment checking is on.
#XMA SIMD floating-point exception that MXCSR does not mask occurs, and CR4.OSXMMEXCPT is 1.

Notes

The memory operand, 4 or 8 bytes, may sit at any address: there is no alignment rule for #GP. A misaligned operand raises #AC(0) only when alignment checking is enabled at privilege level 3.

Unmasked SIMD floating-point exceptions raise #XM, or #UD while CR4.OSXMMEXCPT is 0, as in SSE_TYPE_2.

The manual’s page for MINSS refers it to the Type 2 table, while the manual’s list of instructions by class (Table 2-15) and XED put MINSS here, with the other scalar instructions.

  • avx-type-3: VEX-encoded floating-point arithmetic on scalars and other operands smaller than 16 bytes, such as VADDSS, VCOMISD and the scalar FMA instructions, which Intel's manual calls Exceptions Type 3.
  • SSE_TYPE_2: Legacy SSE floating-point arithmetic on full 16-byte vectors, such as ADDPS, SQRTPD and CVTPS2DQ, which Intel's manual calls Exceptions Type 2.
  • SSE_TYPE_5: Legacy SSE moves, inserts, extracts and conversions on operands smaller than 16 bytes without floating-point exceptions, such as MOVD, PINSRW and PMOVZXBW, which Intel's manual calls Exceptions Type 5.

Instructions

Intel XED puts forms of 31 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

SSE

SSE2

SSE4.1

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.3, Table 2-20; Section 2.5, Tables 2-14 and 2-15; Chapter 4, MINSS.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.