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SSE

SSE_TYPE_4 exception class

Legacy SSE instructions with a 16-byte memory operand and no floating-point exceptions, such as PADDD, PSHUFB, ANDPS and AESENC, which Intel's manual calls Exceptions Type 4.

Class
SSE_TYPE_4 in Intel XED
Applies to
Legacy encodings, without a VEX or EVEX prefix, including those of AES-NI, GFNI, PCLMULQDQ and SHA.
Instructions
139 mnemonics, 274 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDThe operating system has not enabled SSE: CR0.EM is 1 or CR4.OSFXSR is 0.
#UDThe instruction has a LOCK prefix (F0).
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A 16-byte memory operand starts at an address that is not a multiple of 16.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.

Notes

A 16-byte memory operand must be aligned, with the exceptions that the manual names: LDDQU and the string compares PCMPESTRI, PCMPESTRM, PCMPISTRI and PCMPISTRM accept any address, and so does MASKMOVDQU, which stores to the address in DI, EDI or RDI. XED gives MOVUPS, MOVUPD and MOVDQU, which the manual also exempts, a class of their own (SSE_TYPE_4M).

The class has neither #XM nor #AC.

  • avx-type-4: VEX-encoded integer, logical, shuffle and cryptographic instructions without floating-point exceptions, such as VPADDD, VPSHUFB and VAESENC, which Intel's manual calls Exceptions Type 4.
  • SSE_TYPE_4M: The legacy unaligned moves MOVUPS, MOVUPD and MOVDQU, which Intel's manual refers to Exceptions Type 4 but exempts from its alignment rule.
  • SSE_TYPE_7: Legacy SSE instructions without a memory operand or floating-point exceptions, such as MOVMSKPS, PSLLDQ and the shifts by an immediate count, which Intel's manual calls Exceptions Type 7.
  • mmx-mem: MMX instructions on MMX registers and 8-byte memory operands, such as PADDB, PMADDWD and PSHUFW, which Intel's manual lists as SIMD/MMX instructions with a memory reference.

Instructions

Intel XED puts forms of 139 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

SSE

SSE2

SSE3

SSSE3

SSE4.1

SSE4.2

AES-NI

PCLMULQDQ

SHA

GFNI

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.4, Table 2-21; Section 2.5, Tables 2-14 and 2-15; Chapter 4, MASKMOVDQU.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.