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SSE

SSE_TYPE_4M exception class

The legacy unaligned moves MOVUPS, MOVUPD and MOVDQU, which Intel's manual refers to Exceptions Type 4 but exempts from its alignment rule.

Class
SSE_TYPE_4M in Intel XED
Applies to
Legacy encodings of MOVUPS, MOVUPD and MOVDQU.
Instructions
3 mnemonics, 12 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDThe operating system has not enabled SSE: CR0.EM is 1 or CR4.OSFXSR is 0.
#UDThe instruction has a LOCK prefix (F0).
#UDThe processor lacks the instruction’s extension: its CPUID feature flag is 0.
#NMCR0.TS (task switched, bit 3) is 1.
#SS(0)A memory operand addressed through SS lies outside the stack segment.
#SS(0)A memory operand addressed through SS has a non-canonical address.
#GP(0)A memory operand in the CS, DS, ES, FS or GS segment has an effective address that the segment does not allow, such as one beyond its limit.
#GP(0)A memory operand has a non-canonical address.
#GP(0)A memory operand extends past offset FFFFh of its segment.
#PF(fault-code)Accessing a memory operand causes a page fault.

Notes

These are the conditions of Exceptions Type 4 without its alignment rule: the manual states that a misaligned memory operand of these moves raises no #GP. XED gives them a class of their own.

The manual’s pages for MOVUPS and MOVUPD add that their treatment of #AC varies, although the Type 4 table has no #AC row.

  • SSE_TYPE_4: Legacy SSE instructions with a 16-byte memory operand and no floating-point exceptions, such as PADDD, PSHUFB, ANDPS and AESENC, which Intel's manual calls Exceptions Type 4.
  • SSE_TYPE_1: Legacy SSE moves that need a 16-byte aligned memory operand, such as MOVAPS and MOVNTDQ, which Intel's manual calls Exceptions Type 1.
  • avx-type-4M: The VEX-encoded unaligned moves VMOVUPS, VMOVUPD and VMOVDQU, which Intel's manual refers to Exceptions Type 4 with one more reason for #UD.

Instructions

Intel XED puts forms of 3 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

SSE

SSE2

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Section 2.5.4, Table 2-21; Chapter 4, MOVDQU, MOVUPD and MOVUPS.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.