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MSR instructions

USER-MSR-EVEX exception class

USER-MSR-EVEX is the APX specification's exception class for URDMSR and UWRMSR in their EVEX encoding, with the MSR address in a register or an immediate and the registers R16 to R31 available.

Class
USER-MSR-EVEX in Intel XED
Applies to
The EVEX encodings of URDMSR and UWRMSR (USER_MSR with APX): the register forms in map 4 and the immediate forms in map 7.
Instructions
2 mnemonics, 4 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: URDMSR and UWRMSR exist only in 64-bit mode.
#UDA LOCK, 66H, F2H, F3H or REX prefix comes before the EVEX prefix.
#UDEVEX.W or EVEX.L is 1, or EVEX.V4 and EVEX.vvvv are not all 1s.
#UDA bit of the last EVEX payload byte other than V4 is 1.
#UDModRM.mod is not 11B or EVEX.U is 0: the operands are registers.
#UDXCR0 bit 19 (APX) or CR4.OSXSAVE is 0: the operating system has not enabled APX.
#UDCPUID reports no APX_F or no USER_MSR.
#UDThe operating system has not enabled the instructions: bit 0 (ENABLE) of IA32_USER_MSR_CTL is 0.
#GP(0)The MSR address is 4000H or above: bits 63:14 are not all zero.
#GP(0)The MSR’s bit in the operating system’s bitmap is 0: the URDMSR half of the bitmap for URDMSR, the UWRMSR half for UWRMSR.
#GP(0)UWRMSR only: the MSR is not one that UWRMSR may write.
#GP(0)The instruction runs inside an enclave and the access would cause a VM exit.
#GP(0)RDMSR or WRMSR of the same MSR would raise #GP(0), for example for reserved bits in the value.

Notes

The #GP(0) for an access that would cause a VM exit inside an enclave is in the APX table only; the SDM’s pages for the legacy and VEX forms do not list it. The operating system’s bitmap works as described for USER-MSR-LEGACY.

  • USER-MSR-LEGACY: USER-MSR-LEGACY is XED's name for the exceptions of URDMSR and UWRMSR with the MSR address in a register, which Intel documents on the instruction pages rather than as a named class.
  • USER-MSR-VEX: USER-MSR-VEX is XED's name for the exceptions of the VEX-encoded URDMSR and UWRMSR with an immediate MSR address, which Intel documents on the instruction pages rather than as a named class.
  • MSR-IMM-EVEX: MSR-IMM-EVEX is the APX specification's exception class for RDMSR and WRMSRNS with an immediate MSR address in their EVEX encoding, which lets the register operand be R16 to R31.

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

APX

Sources

  1. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025): Section 4.2.22, Table 4.23.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): URDMSR and UWRMSR, 64-Bit Mode Exceptions.
  3. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.