x86-64.net

MSR instructions

USER-MSR-LEGACY exception class

USER-MSR-LEGACY is XED's name for the exceptions of URDMSR and UWRMSR with the MSR address in a register, which Intel documents on the instruction pages rather than as a named class.

Class
USER-MSR-LEGACY in Intel XED
Applies to
The legacy encodings of USER_MSR: URDMSR r64, r64 (F2 0F 38 F8) and UWRMSR r64, r64 (F3 0F 38 F8).
Instructions
2 mnemonics, 2 forms
Data
Intel XED v2026.08.23

Exception conditions

When an instruction of the class raises each exception, and in which processor modes. Protected mode includes compatibility mode. How to read the table.
ExceptionRealVirtual-8086Protected64-bitCondition
#UDAlways: URDMSR and UWRMSR exist only in 64-bit mode.
#UDA LOCK prefix is used.
#UDCPUID reports no USER_MSR (CPUID.(EAX=07H,ECX=1):EDX bit 15).
#UDThe operating system has not enabled the instructions: bit 0 (ENABLE) of IA32_USER_MSR_CTL is 0.
#GP(0)The MSR address in the register is 4000H or above: bits 63:14 are not all zero.
#GP(0)The MSR’s bit in the operating system’s bitmap is 0: the URDMSR half of the bitmap for URDMSR, the UWRMSR half for UWRMSR.
#GP(0)UWRMSR only: the MSR is not one that UWRMSR may write; so far that is only IA32_UARCH_MISC_CTL (1B01H).
#GP(0)RDMSR or WRMSR of the same MSR would raise #GP(0), for example for reserved bits in the value.

Notes

No Intel document defines this class. The rows come from the exception sections of URDMSR and UWRMSR in SDM Volume 2, which cover the register and the immediate forms together.

The operating system decides which MSRs user code may read or write. IA32_USER_MSR_CTL (MSR 1CH) holds the enable bit and the address of a 4-KByte bitmap with one bit per MSR from 0 to 3FFFH: its low 2 KBytes allow URDMSR, its high 2 KBytes UWRMSR. The processor reads the bitmap with supervisor rights, whatever the CPL, and UWRMSR does not serialize, like WRMSRNS.

  • USER-MSR-VEX: USER-MSR-VEX is XED's name for the exceptions of the VEX-encoded URDMSR and UWRMSR with an immediate MSR address, which Intel documents on the instruction pages rather than as a named class.
  • USER-MSR-EVEX: USER-MSR-EVEX is the APX specification's exception class for URDMSR and UWRMSR in their EVEX encoding, with the MSR address in a register or an immediate and the registers R16 to R31 available.

Instructions

Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.

USER_MSR

Sources

  1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): URDMSR and UWRMSR, Description and Exceptions.
  2. Intel XED v2026.08.23 (commit 0bcb6237345c): the exception class of each instruction form.

The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.