MSR instructions
USER-MSR-VEX exception class
USER-MSR-VEX is XED's name for the exceptions of the VEX-encoded URDMSR and UWRMSR with an immediate MSR address, which Intel documents on the instruction pages rather than as a named class.
- Class
USER-MSR-VEXin Intel XED- Applies to
- The VEX encodings (map 7) of
URDMSR r64, imm32andUWRMSR imm32, r64(USER_MSR). - Instructions
- 2 mnemonics, 2 forms
- Data
- Intel XED v2026.08.23
Exception conditions
| Exception | Real | Virtual-8086 | Protected | 64-bit | Condition |
|---|---|---|---|---|---|
#UD | yes | yes | yes | no | Always: URDMSR and UWRMSR exist only in 64-bit mode. |
#UD | no | no | no | yes | A LOCK prefix is used. |
#UD | no | no | no | yes | CPUID reports no USER_MSR (CPUID.(EAX=07H,ECX=1):EDX bit 15). |
#UD | no | no | no | yes | The operating system has not enabled the instructions: bit 0 (ENABLE) of IA32_USER_MSR_CTL is 0. |
#GP(0) | no | no | no | yes | The MSR address in the immediate is 4000H or above. |
#GP(0) | no | no | no | yes | The MSR’s bit in the operating system’s bitmap is 0: the URDMSR half of the bitmap for URDMSR, the UWRMSR half for UWRMSR. |
#GP(0) | no | no | no | yes | UWRMSR only: the MSR is not one that UWRMSR may write; so far that is only IA32_UARCH_MISC_CTL (1B01H). |
#GP(0) | no | no | no | yes | RDMSR or WRMSR of the same MSR would raise #GP(0), for example for reserved bits in the value. |
Notes
No Intel document defines this class. The rows come from the exception sections of URDMSR and UWRMSR in SDM Volume 2, which cover the register and the immediate forms together and name no #UD conditions for the VEX fields. The operating system’s bitmap works as described for USER-MSR-LEGACY.
Related classes
Instructions
Intel XED puts forms of 2 mnemonics in this class, listed here by extension. Where a mnemonic also has forms of other classes, its link leads to its first form of this one.
USER_MSR
Sources
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): URDMSR and UWRMSR, Description and Exceptions.
- Intel XED v2026.08.23 (commit
0bcb6237345c): the exception class of each instruction form.
The list of instructions is derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted it. The text is our own.