EXTRACTPS instruction (SSE4.1)

EXTRACTPS copies one single out of an XMM register, to four bytes of memory or to a 32-bit general-purpose register. The low two bits of the immediate pick the element and the rest are ignored: on Zen 5, extractps ecx, xmm7, 0B6h copied element 2 and cleared bits 63:32 of RCX, as every write to a 32-bit register does.

Bits, not a number

The register form copies the bit pattern: 1.0 arrives as 3F800000h, not as the integer 1. The intrinsic says as much in its type, int _mm_extract_ps(__m128 a, int i), which returns those bits; code that wants the float itself has to move them back, and the compilers see through that: going through memcpy to a float, GCC 14 and Clang 23 at -O2 drop EXTRACTPS for one shuffle that leaves the element in XMM0. For a conversion to an integer value, CVTTSS2SI or CVTSS2SI is the instruction. EXTRACTPS cannot write an XMM register; moving an element within the vector registers is the job of SHUFPS or INSERTPS.

Storing single elements

The memory form is where compilers use it on their own. With -msse4.1, both compile *p = v[1] to extractps dword ptr [rdi], xmm0, 1, and storing the four elements of a vector to four scattered addresses to a MOVSS for element 0 and three EXTRACTPS. For the SSE2 baseline, each of those three costs a shuffle into element 0 and a MOVSS. Intel’s optimization manual shows the same pattern for doublewords with PEXTRD (Section 6.4.8); both write exactly four bytes, with no alignment requirement.

VEXTRACTPS, the VEX and EVEX form, also reads only an XMM register: an element in the upper half of a YMM register needs VEXTRACTF128 first. PEXTRB describes the byte form and the zero extension of the integer extracts. AMD’s Zen 5 guide lists EXTRACTPS as two macro-ops, where INSERTPS takes one.

Forms

Every encoding of EXTRACTPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`EXTRACTPS m32, xmm, imm8` EXTRACTPS_MEMd_XMMps_IMMb	`66 0F 3A 17 /r ib`	SSE4.1
`EXTRACTPS r32, xmm, imm8` EXTRACTPS_GPR32d_XMMdq_IMMb	`66 0F 3A 17 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: single imm8 of xmm2 goes to m32.

Example: imm8 = 0x02.

With imm8 = 0x02, m32 receives single 2 of xmm2: a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(xmm2.d[imm8 & 3])  # a register: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`EXTRACTPS r/m32, xmm, imm8`
`r/m32`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to EXTRACTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_extract_ps` `int _mm_extract_ps(__m128 X, const int N)`	`EXTRACTPS r32, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Bits, not a number#

Storing single elements#

Related instructions#