x86-64.net

Instruction

EXTRQ

Extracts a bit field, whose length and position an immediate or a register gives, from the low quadword of an XMM register; SSE4a.

An AMD extension: Intel processors do not have this instruction.

Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of EXTRQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
EXTRQ xmm, imm8, imm8 EXTRQ_XMMq_IMMb_IMMb66 0F 78 /0 ib ibSSE4A
EXTRQ xmm, xmm EXTRQ_XMMq_XMMdq66 0F 79 /rSSE4A

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, imm8, imm8
xmm, xmm
Piledriver3 / 1.5FPMAL FPU0 FPU1
Zen2 / 1FPU1 FPU2
Zen 23 / 1FPU1 FPU2
Zen 3, Zen 43 / 0.5FP1 FP2 FP45
Jaguar1 / 0.5FPU0 FPU1 VALU0 VALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

EXTRQ xmm, imm8, imm8
n = length & 63                  # the field: n bits
p = index & 63                   # from bit p
if n == 0:
    n = 64
x = xmm1.q[0]
if p + n <= 64:
    xmm1.q[0] = low(x >> p, n)   # to bit 0, zero-extended
else:
    xmm1.q[0] = UNDEFINED        # Zen 5: as above, bits 63:p
xmm1.q[1] = UNDEFINED            # Zen 5: 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 7 cases.

EXTRQ xmm, xmm
n = xmm2.b[0] & 63               # the field: n bits
p = xmm2.b[1] & 63               # from bit p
if n == 0:
    n = 64
x = xmm1.q[0]
if p + n <= 64:
    xmm1.q[0] = low(x >> p, n)   # to bit 0, zero-extended
else:
    xmm1.q[0] = UNDEFINED        # Zen 5: as above, bits 63:p
xmm1.q[1] = UNDEFINED            # Zen 5: 0
# the other bits of xmm2 are ignored
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
EXTRQ xmm, imm8, imm8
xmmexplicitwrite
imm8explicitread
imm8explicitread
EXTRQ xmm, xmm
xmmexplicitwrite
xmmexplicitread

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to EXTRQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_extract_si64 __m128i _mm_extract_si64(__m128i __x, __m128i __y)

EXTRQ xmm, xmm Legacy -msse4a

EXTRQ xmm, xmm Legacy -msse4a -mavxwith AVX enabled

_mm_extracti_si64 __m128i _mm_extracti_si64(__m128i x, const char len, const char idx)

EXTRQ xmm, imm8, imm8 Legacy -msse4a

EXTRQ xmm, imm8, imm8 Legacy -msse4a -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE4a

SSE4A
CPUID.80000001H:ECX[6] SSE4A

K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More SSE4a instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit, 256-Bit, and 512-Bit Media Instructions (26568, rev. 3.27, July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.