FABS instruction (x87)

FABS clears the sign bit of ST(0), bit 79, and changes nothing else. It works on the bits, not on the value: -0 becomes +0, -infinity +infinity, and a negative NaN the same NaN with a positive sign. FCHS flips that bit instead.

No exceptions

Since nothing is computed, FABS raises no floating-point exception other than a stack underflow when ST(0) is empty (IE and SF, and with IE masked the QNaN indefinite in its place). Zen 5’s cases show what that means for the operands that make arithmetic fault:

An SNaN keeps its bits but the sign, and stays signaling: no IE, even with IE unmasked. An FADD of it would raise IE and return it quieted.
A denormal raises no DE, and stays denormal.
Unsupported encodings, such as an unnormal or a pseudo-NaN, are kept without IE.

C1 is cleared. Intel’s manual leaves C0, C2 and C3 undefined; Zen 5 kept them.

From C

GCC 14 and Clang 23 at -O2 compile fabsl(x) on a long double to an FLD of the argument and FABS. For fabsf and fabs in 64-bit code, where floats and doubles live in XMM registers, both compilers clear the sign with an ANDPS or ANDPD against a constant mask instead; with -m32 -march=i386, where they live on the x87 stack, both emit FABS again.

AMD’s Zen 5 guide lists FABS, like FCHS, as one macro-op that runs on either of two FP pipes, two per cycle.

Forms

Every encoding of FABS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FABS` FABS	`D9 E1`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = st0 & ~(1 << 79)       # the sign bit cleared, whatever the
                                 # value, NaNs too: no exception
    c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 13 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FABS`
`ST(0)`	implicit	read, write
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

No exceptions#

From C#