FADD instruction (x87)

FADD adds two values on the x87 register stack, or a single or double from memory to ST(0). One of the operands is always ST(0): the forms fadd st, st(i) and fadd st(i), st differ only in which register receives the sum, and the memory forms add to ST(0). FADDP adds into ST(i) and pops, which is how most sums end, and FIADD adds an integer from memory.

Compilers reach for FADD where a value is already on the stack. GCC 14 and Clang 23 at -O2 compile x * 2 on a long double to fadd st, st(0), doubling x without a constant, and a + b with a double b, which arrives in XMM0, to a store of XMM0 to the stack and fadd QWORD PTR of it: the x87 cannot read an XMM register.

Precision and rounding

The memory operand is converted to the 80-bit format exactly, so the sum is rounded only once: to the precision of PC, 24, 53 or 64 bits of significand, in the direction of RC. C1 tells which way it went: 1 if the result was rounded up. PC applies to the additions, subtractions, multiplications and divisions and to FSQRT, nothing else. FNINIT sets it to 64 bits, which Intel’s manual names the default. The exponent range stays the 80-bit format’s whatever PC says, so a sum that would overflow a double does not overflow here.

In 32-bit code, where GCC 14 does double arithmetic on the x87 with __FLT_EVAL_METHOD__ 2, a double sum is rounded first to 64 bits of significand and again when it is stored as a double; the two roundings can differ from the one an SSE2 ADDSD makes.

Special cases

Infinities of opposite signs give an invalid operation: IE is set, and with it masked the result is the QNaN indefinite. A denormal operand raises DE, and an empty operand register is a stack underflow, which with IE masked also gives the indefinite.

AMD’s Zen 5 guide lists FADD as one macro-op, on one pipe, with one started each cycle.

Forms

Every encoding of FADD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FADD m32fp` FADD_MEMmem32real	`D8 /0`	FPU
`FADD ST(0), st(i)` FADD_ST0_X87	`D8 C0+i`	FPU
`FADD m64fp` FADD_MEMm64real	`DC /0`	FPU
`FADD st(i), ST(0)` FADD_X87_ST0	`DC C0+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(dest) or empty(src):
    underflow()                  # IE, SF, C1 = 0
    dest.write(INDEFINITE)       # the QNaN indefinite
else:
    dest.write(add(dest, src))   # C1 = 1 if rounded up
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 58 cases.

Memory forms

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = add(st0, src)          # a single or double: exact in the
                                 # 80-bit format, then the sum rounded
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 23 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FADD m32fp` `FADD m64fp`
`m32/64fp`	explicit	read
`ST(0)`	implicit	read, write
`x87 status word`	implicit	write
`FADD ST(0), st(i)`
`ST(0)`	explicit	read, write
`st(i)`	explicit	read
`x87 status word`	implicit	write
`FADD st(i), ST(0)`
`st(i)`	explicit	read, write
`ST(0)`	explicit	read
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Precision and rounding#

Special cases#