FBLD instruction (x87)

FBLD reads a packed decimal integer of ten bytes, converts it to the 80-bit format and pushes it onto the x87 register stack. FBSTP stores one. In the format, the low nine bytes hold 18 decimal digits, two per byte with the more significant digit in the high nibble, the least significant byte first; the tenth byte holds the sign in its top bit, and its other seven bits are unused. A negative number is its magnitude with the sign bit set, not a complement.

Always exact

The largest magnitude, 10^18 - 1, needs 60 bits, so every value fits the 64-bit significand: FBLD never rounds and never sets PE, and -0 stays -0. Zen 5 loaded the eighteen nines as 999999999999999999 in full even with PC at 24 bits. That makes FBLD followed by FISTP with a 64-bit operand a conversion from decimal digits to a binary integer in two instructions, and FILD followed by FBSTP the way back.

Bytes outside the format

Both manuals assume digits 0 to 9; Intel’s says that FBLD does not check them and that other nibbles give an undefined result. Zen 5 raised no exception and weighed each nibble by its place, digits of 10 to 15 included:

the unused bits did not matter: a tenth byte of 7FH loaded a plus sign;
the byte 0AH loaded 10, 9AH loaded 100, and 0FH 0FH loaded 1515;
the packed decimal indefinite, FFFFH C0H and seven zero bytes, which FBSTP stores for an invalid operation, is no NaN to FBLD: Zen 5 loaded it as -1662000000000000000, from the “digits” 15, 15 and 12 at the top.

So a round trip through memory does not keep the indefinite: test the stored bytes instead.

Flags and a full stack

FBLD cleared C1 and kept C0, C2 and C3, which both manuals leave undefined. As a push it needs ST(7) empty; when it was not, Zen 5 pushed the QNaN indefinite with IE masked, setting IE, SF and C1, and with IE unmasked changed no register, the #MF coming at the next waiting instruction.

AMD’s Zen 5 guide lists FBLD as microcoded.

Forms

Every encoding of FBLD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FBLD m80bcd` FBLD_ST0_MEMmem80dec	`DF /4`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not empty(st7):                   # the register the push fills
    overflow()
    push(INDEFINITE)
else:
    push(from_bcd(src))              # exact, -0 too; bits 78:72 are
    c1 = 0                           # ignored; a digit above 9 gives an
                                     # UNDEFINED value (Zen 5 weighs it
                                     # as a digit: 0x9A is 100)
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 21 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FBLD m80bcd`
`m80bcd`	explicit	read
`x87 register stack`	implicit	push
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Always exact#

Bytes outside the format#

Flags and a full stack#