FBSTP instruction (x87)

FBSTP rounds ST(0) to an integer as RC says, stores it as an 18-digit packed decimal integer of ten bytes, the format that FBLD’s page describes, and pops. There is no form that keeps ST(0), and no other size. With FILD first, it turns a binary integer below 10^18 into decimal digits in two instructions.

Rounding

Zen 5 rounded the halves this way, with PE each time:

ST(0)	to nearest	down	up	toward zero
2.5	2	2	3	2
-0.5	-0	-1	-0	-0

The sign survives a result of zero: -0.5 and -0.3 to nearest both stored -0, a sign byte of 80H. C1 says whether the magnitude was rounded up: set for 1.5 to 2, -1.5 to -2 and 2.5 to 3, clear for 2.5 to 2. A denormal raises no DE here: the smallest one stored +0 with PE alone.

The indefinite

Whether a value fits is decided after rounding. Zen 5 stored 999999999999999999 in full, but 999999999999999999.5 rounds to 10^18 when rounding to nearest, and that, like 10^18 itself, was an invalid operation (IE). So were the infinities, the largest finite numbers, unsupported encodings and every NaN, quiet ones included, unlike FST, which passes a QNaN on. With IE masked, FBSTP stores the packed decimal indefinite, the bytes 00H x7, C0H, FFH, FFH, and pops; an empty ST(0) does the same, with SF. Read back with FBLD, the indefinite is a number, not a NaN, as FBLD’s page shows.

With IE unmasked, Zen 5 stored nothing and did not pop, and #MF came at the next waiting instruction. An unmasked PE did not stop it: 2.5 was stored as 2 and popped, and then came the #MF.

AMD’s Zen 5 guide lists FBSTP as microcoded.

Forms

Every encoding of FBSTP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FBSTP m80bcd` FBSTP_MEMmem80dec_ST0	`DF /6`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()
    v = INDEFINITE
else:
    v = st0
dest.write(to_bcd(v))                # rounded by RC, the sign kept
                                     # (-0.3 gives -0); past 18
                                     # digits, a NaN or an infinity
                                     # give the BCD indefinite, with IE
pop()
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 54 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FBSTP m80bcd`
`m80bcd`	explicit	write
`x87 register stack`	implicit	pop
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Rounding#

The indefinite#