FCHS instruction (x87)

FCHS flips the sign bit of ST(0), bit 79, and leaves the other 79 bits as they are. It is the x87’s negation: 1 becomes -1, +0 becomes -0, +infinity -infinity. FABS is its twin, clearing the bit instead, and its page’s account of the special operands holds here as well.

Negation is not subtraction from zero

C’s -x is FCHS: on a long double, GCC 14 and Clang 23 at -O2 load the argument with FLD and emit FCHS, and with -m32 -march=i386, where floats and doubles live on the x87 stack too, they do the same for those. 0.0L - x stays a subtraction, an FLDZ and an FSUBRP after the load of x (GCC with -m32 loads the zero first and subtracts with FSUBP), and the two differ for zeros: 0 - (+0) is +0 under the default rounding, while FCHS of +0 gives -0. The compilers may only turn one into the other where the sign of zero cannot matter. In 64-bit code a float or double is negated in its XMM register with an XOR against a mask of the sign bit, XORPS or XORPD.

Nothing to signal

FCHS computes nothing, so it raises no floating-point exception for any value it can read; Zen 5’s cases show:

An SNaN changes sign and stays signaling, without IE even when IE is unmasked; an arithmetic instruction would raise IE and quiet it.
A denormal changes sign and stays denormal, without DE.
Unnormals and pseudo-NaNs, which arithmetic rejects with IE, have their sign flipped and nothing else.

Only an empty ST(0) is an error: a stack underflow sets IE and SF and, with IE masked, writes the QNaN indefinite; with IE unmasked Zen 5 left the register empty and set ES, so that the next waiting instruction raises #MF. In both cases C1 is cleared, as it is after every FCHS. Intel’s manual leaves C0, C2 and C3 undefined; Zen 5 kept them.

AMD’s Zen 5 guide lists FCHS as one macro-op on either of two FP pipes, two per cycle, like FABS.

Forms

Every encoding of FCHS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FCHS` FCHS	`D9 E0`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = st0 ^ 1 << 79          # the sign bit flipped, whatever the
                                 # value, NaNs too: no exception
    c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 13 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FCHS`
`ST(0)`	implicit	read, write
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Negation is not subtraction from zero#

Nothing to signal#