FCMOVB instruction (x87)

FCMOVB copies ST(i) to ST(0) when CF is set, B standing for below. It is one of eight x87 conditional moves, the counterpart of CMOVcc for the register stack: FCMOVE tests ZF, FCMOVBE CF or ZF, FCMOVU PF, and FCMOVNB, FCMOVNE, FCMOVNBE and FCMOVNU their negations. The destination is always ST(0), and the source always a register.

Only the conditions of FCOMI

Those eight are exactly the conditions that FCOMI and FUCOMI produce, which are also those of an unsigned integer compare. Nothing tests SF or OF, so there is no FCMOVL or FCMOVG. GCC 14 at -O2 shows the uses:

with -ffast-math, fmaxl(a, b) becomes two FLDs leaving a in ST(0), fcomi st, st(1), fcmovb st, st(1), which takes b when a is below it, and fstp st(1); without it, a call of fmaxl;
x < y ? a : b on unsigned integers and long doubles becomes CMP, the two loads and FCMOVNB; on signed integers, CMP and a JGE around the second load.

Clang 23 also pairs FUCOMI with an FCMOVcc for compares of long doubles, but for an integer condition, signed or not, it selects the address with CMOVL or CMOVB and loads once.

Both registers must be full

Intel’s manual moves ST(i) only when the condition holds and lists a stack underflow as FCMOVcc’s only exception. Zen 5 checked both registers whatever the flags said: with CF clear and ST(i) empty, it still raised IE and SF and, with IE masked, replaced ST(0) by the QNaN indefinite. When the move happens the value is copied as it is, so an SNaN arrives still signaling, with no exception. C1 is cleared on a stack underflow; otherwise Zen 5 left C0 to C3 as they were.

Cost

The FCMOVcc instructions came with the P6 family, and a processor has them when CPUID reports both CMOV and FPU. Intel’s optimization manual names CMOV and FCMOV as ways to remove unpredictable branches (Section 3.4.1.1). AMD’s Zen 5 guide, however, lists every FCMOVcc as microcoded, where FCOMI is two macro-ops.

Forms

Every encoding of FCMOVB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FCMOVB ST(0), st(i)` FCMOVB_ST0_X87	`DA C0+i`	CMOV + FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(dest) or empty(src):
    underflow()
    dest.write(INDEFINITE)
elif cf:
    dest.write(src)                  # as it is: an SNaN raises nothing
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FCMOVB ST(0), st(i)`
`ST(0)`	explicit	conditional write
`st(i)`	explicit	read
`x87 status word`	implicit	write
`RFLAGS`	implicit	read

Flags

T tested, M modified, U undefined; blank: not affected. How to read.

CF	C0	C1	C2	C3
All forms
T	U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`FCMOV` x87	CMOV + FPU `CPUID.01H:EDX[15]` CMOV `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Only the conditions of FCOMI#

Both registers must be full#

Cost#