FCOM instruction (x87)

FCOM compares ST(0) with another x87 register, ST(1) when none is named, or with a single or a double in memory, which it widens exactly first; there is no 80-bit memory form. The answer goes into the condition codes of the x87 status word, not into RFLAGS:

ST(0) is	C3	C2	C0
greater	0	0	0
less	0	0	1
equal (-0 equals +0)	1	0	0
unordered	1	1	1

C1 is cleared. FCOMP pops ST(0) after the compare and FCOMPP pops twice; FUCOM and its kin differ only for QNaNs, and FICOM compares with an integer.

Getting the answer out

Branching on the condition codes takes two more instructions: FNSTSW AX copies the status word into AX, where C0, C2 and C3 land in bits 0, 2 and 6 of AH, the places of CF, PF and ZF, and SAHF or a TEST of AH follows. GCC 14 at -O2 with -m32 -march=i386 compiles a < lo ? lo : a on doubles to two FLDs, fcom st(1), which keeps both values for the result, fnstsw ax and test ah, 69 (45H, the three codes): none set means lo is greater. Clang 23 uses FUCOM, SAHF and JA. From the P6 family on, FCOMI writes ZF, PF and CF directly, and compilers use it whenever the target has it. AMD’s Zen 5 guide lists FCOM as one macro-op and advises against putting other instructions between the compare and the FNSTSW (Section 2.11.3).

NaNs and invalid operands

Any NaN, quiet or signaling, is an invalid operation (IE), and so is an unsupported encoding; with IE masked the result is unordered.
A denormal operand raises DE, a denormal single or double in memory included.
An empty register is a stack underflow: IE and SF, C1 = 0, unordered.

Intel’s manual says that an unmasked IE leaves the condition codes unset. Zen 5 set them to unordered anyway, and #MF came at the next waiting instruction; with DE unmasked it set them to the compare’s result. FCOMI does the same with RFLAGS on Zen 5.

XED also decodes DC D0+i as FCOM, an encoding it marks as undocumented; Zen 5 ran it as FCOM ST(i).

Forms

Every encoding of FCOM that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FCOM m32fp` FCOM_ST0_MEMmem32real	`D8 /2`	FPU
`FCOM m64fp` FCOM_ST0_MEMm64real	`DC /2`	FPU
`FCOM st(i)` FCOM_ST0_X87	`D8 D0+i`	FPU
`FCOM st(i)` undocumented FCOM_ST0_X87_DCD0	`DC D0+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

Memory forms

if empty(st0):
    underflow()
    x = 3                        # unordered
else:
    x = comi(st0, src)           # a single or a double, exactly;
                                 # any NaN raises IE
c3 = x in (2, 3)                 # set with IE or DE unmasked too
c2 = x == 3
c0 = x in (1, 3)
c1 = 0

Run on AMD Zen 5 (EPYC 9645): 24 cases.

if empty(st0) or empty(src):
    underflow()
    x = 3                        # unordered
else:
    x = comi(st0, src)           # any NaN raises IE
c3 = x in (2, 3)                 # set with IE or DE unmasked too
c2 = x == 3
c0 = x in (1, 3)
c1 = 0

Run on AMD Zen 5 (EPYC 9645): 42 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FCOM m32fp` `FCOM m64fp`
`m32/64fp`	explicit	read
`x87 status word`	implicit	write
`FCOM st(i)`
`st(i)`	explicit	read
`x87 status word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Getting the answer out#

NaNs and invalid operands#