FCOMI instruction (x87)

FCOMI compares ST(0) with another x87 register and puts the answer in ZF, PF and CF of RFLAGS, where a conditional jump, SETcc, CMOVcc or FCMOVB and its kin can test it at once. The pattern is the one COMISS later took over: ST(0) greater clears all three, less sets CF, equal sets ZF (-0 equals +0), and unordered, a NaN on either side, sets all three. OF, SF and AF are cleared; C0, C2 and C3 stay as they were. FCOMI came with the P6 family, and CPUID reports it through the CMOV bit together with FPU, as AMD’s manual says.

Its kin, and the second pop

FCOMIP pops ST(0) after the compare. FUCOMI and FUCOMIP raise IE only for a signaling NaN, where FCOMI raises it for any NaN. None of them pops both operands, so compiled code pops the other one with fstp st(0). GCC 14 at -O2 compiles a < b on long double to

fld of a, then fld of b,
fcomip st, st(1), which compares b with a,
fstp st(0) and seta al.

As with COMISS, the compilers turn the compare around so that the condition is A or AE, which are false when the result is unordered. For a == b, GCC uses FUCOMIP and checks PF as well as ZF; Clang 23 uses FUCOMIP for both compares.

Before FCOMI

Older processors had to move the condition codes through AX: a compare such as FCOM, then FNSTSW AX, then SAHF or a TEST of AH. Compilers still do that for such targets: Clang 23 with -m32 -march=i386 compiles a < b on doubles to FUCOMPP, fnstsw ax, SAHF and SETA.

The manuals and Zen 5

Intel’s manual has FCOMI clear C1 always; AMD’s clears it only for a stack underflow, and leaves it otherwise. Zen 5 does as AMD says.
Intel’s manual says that an unmasked invalid-operation exception leaves ZF, PF and CF alone. Zen 5 set all three, reporting unordered, and #MF came at the next waiting instruction.

AMD’s Zen 5 guide lists FCOMI, FCOMIP, FUCOMI and FUCOMIP as two macro-ops each.

In the optimization guide

What the optimization guide says about FCOMI, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Vectors and cryptography: Prefer SSE to x87, and fcomi to fcom with fnstsw, on these cores.

Forms

Every encoding of FCOMI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FCOMI ST(0), st(i)` FCOMI_ST0_X87	`DB F0+i`	CMOV + FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(src1) or empty(src2):
    underflow()
    x = 3                            # unordered
else:
    x = comi(src1, src2)             # any NaN raises IE
zf = x in (2, 3)                     # set with IE or DE unmasked too
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0                     # C0 to C3 are kept, C1 but after
                                     # a stack fault

Run on AMD Zen 5 (EPYC 9645): 25 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FCOMI ST(0), st(i)`
`ST(0)`	explicit	read
`st(i)`	explicit	read
`x87 status word`	implicit	write
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF	C1
All forms
0	0	M	0	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`FCOMI` x87	CMOV + FPU `CPUID.01H:EDX[15]` CMOV `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Its kin, and the second pop#

Before FCOMI#

The manuals and Zen 5#