Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

FCOS replaces ST(0), an angle in radians, by its cosine. It shares everything that FSIN’s page says about the range and the x87’s internal pi: an angle of 2^63 or more in magnitude sets C2 and leaves ST(0) as it was, and a smaller one is reduced by a pi of 66 bits before the cosine is approximated. Code that needs the sine and the cosine of one angle uses FSINCOS, which reduces it once and leaves the cosine on top.

Where the error shows

The cosine is small near the odd multiples of pi/2, so that is where the 66-bit pi runs out, not near 0 as for the sine. For pi/2 rounded to 64 bits, whose true cosine is about -2.508 * 10^-20, Zen 5 returned exactly -2^-65, about -2.711 * 10^-20, 8 percent away; for 3 * pi / 2 rounded to 64 bits it was 3 percent away. For reduced arguments the page’s pseudocode checks Zen 5’s results within 1 ulp (1.5 when not rounding to nearest), and the worst of its 28 recorded results was 0.48 ulp to nearest and 0.90 in the other modes.

Small angles and the other edges

  • The cosine of +0 and of -0 is +1, exact. For any angle too small to move the cosine below 1 in 64 bits, Zen 5 returned 1 with PE and C1 set (rounded up), and DE for a denormal.
  • Infinities, SNaNs and unsupported encodings, such as an unnormal, are invalid operations: IE, and with it masked the QNaN indefinite. A QNaN passes through without an exception.
  • Zen 5 set C2 for exactly 2^63 and computed the cosine of the next smaller number.

From C

GCC 14 at -O2 compiles cosl(x) on a long double to a call of the library, and the pair sinl(x), cosl(x) to one call of sincosl. With -funsafe-math-optimizations (part of -ffast-math) it emits fcos for the first and fsincos for the pair. Clang 23 calls the library in both cases. Neither uses the x87 for cos on a double.

Speed

AMD’s Zen 5 guide lists FCOS, like the other transcendental instructions, as microcoded, and Intel’s optimization manual suggests software implementations where 80 bits are not needed (Section 3.9.1).

Forms

Every encoding of FCOS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
FCOS FCOSD9 FFFPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = st0
big = not less(abs(x), 2 ** 63)  # |x| >= 2^63 (or no number)
if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
    c2 = 0
elif big and is_finite(x):
    c1 = 0                       # out of range: ST(0) stays
    c2 = 1
else:
    st0 = cos(x)                 # within 1 ulp (1.5 when not
    c2 = 0                       # rounding to nearest); Zen 5's 28
                                 # recorded results: 0.48 at most to
                                 # nearest, 0.90 in the other modes
c0 = c3 = UNDEFINED              # Zen 5 keeps them
# cos(x) is the cosine of x * pi / Pi, where Pi is the 66-bit pi by
# which the processor reduces x: near an odd multiple of pi/2 the
# result is far from the cosine of x

Run on AMD Zen 5 (EPYC 9645): 48 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
FCOS
ST(0)implicitread, write
x87 status wordimplicitwrite

Flags

M modified, U undefined; blank: not affected. How to read.
C0C1C2C3
All forms
UMMU

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
X87

FPU
CPUID.01H:EDX[0] FPU

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-330 (FCOS)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  5. AMD64 Architecture Programmer's Manual, Volume 5: 64-Bit Media and x87 Floating-Point Instructions (26569, rev. 3.16, November 2021), Wayback Machine copy of AMD's PDF
  6. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.