FDECSTP instruction (x87)

FDECSTP subtracts 1 from TOP, the 3-bit field of the x87 status word that says which physical register is ST(0); from 0 it wraps to 7. No register’s value or tag changes, so the register that was ST(7) becomes ST(0), with whatever it held, and the old ST(0) becomes ST(1). It is two bytes, D9 F6, and undoes FINCSTP.

Not a push

A push, as in FLD, also subtracts 1 from TOP, but then writes a value into the new ST(0) and tags it valid, and first checks that the register is empty. FDECSTP does neither. On Zen 5, FDECSTP on a stack of three values made an empty register ST(0), and the three values became ST(1) to ST(3). An instruction that reads ST(0) next finds a stack underflow, IE and SF with C1 = 0. FDECSTP followed by FINCSTP, or the other way round, leaves the stack as it was.

No exception of its own

FDECSTP raises no floating-point exception, whatever the tags: Zen 5 moved TOP from 7 to 6 with all eight registers empty, and from 3 to 2 with all eight full. Intel’s manual lists #MF for an unmasked exception pending before it, as for any waiting x87 instruction. Both manuals clear C1 and leave C0, C2 and C3 undefined; in all six of Zen 5’s cases FDECSTP cleared C1 and kept the other three.

AMD’s Zen 5 guide lists FDECSTP as one macro-op, six per cycle, with no FP pipe named.

Forms

Every encoding of FDECSTP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FDECSTP` FDECSTP	`D9 F6`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

top = top - 1                        # from 0 to 7
c1 = 0
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FDECSTP`
`x87 status word`	implicit	read, write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Not a push#

No exception of its own#