FDIV instruction (x87)

FDIV divides, and the dividend’s register receives the quotient: fdiv st, st(i) computes ST(0) / ST(i) into ST(0), fdiv st(i), st computes ST(i) / ST(0) into ST(i), and the memory forms divide ST(0) by a single or double. Since division does not commute, each form has a reversed twin: FDIVR divides the other way round into the same register, and FDIVP and FDIVRP do so into ST(i) and pop. For a / b on two long doubles, GCC 14 at -O2 loads a, then b, and emits fdivp st(1), st; Clang 23 loads them the other way and emits fdivrp st(1), st.

The AT&T names

In AT&T syntax, which GCC emits by default, the register forms with ST(i) as the destination swap the R: GCC’s own AT&T output for that a / b reads fdivrp %st, %st(1), and GNU as 2.44 encodes it as DE F9, which Intel’s manual and objdump -M intel call fdivp st(1), st; likewise fdiv %st, %st(1) is Intel’s fdivr st(1), st. FSUB and FSUBR share the trait. GCC and GNU as agree with each other, so compiled code is right; hand-written AT&T assembly, and listings read across the two syntaxes, are where it bites.

Edge cases

A nonzero finite dividend over zero sets ZE and, with it masked, gives an infinity of the quotient’s sign.
Zero over zero and infinity over infinity are invalid operations: IE, and with it masked the QNaN indefinite.
The quotient is rounded once, to PC’s precision, as RC says; C1 is 1 if it was rounded up.

Speed

Intel’s optimization manual notes that a smaller PC lets the divider finish sooner, at 24 bits fastest, and asks for as few precision changes as possible (Section 3.9.3.2). AMD’s Zen 5 guide lists one FDIV started every five cycles at most, against one FADD or FMUL each cycle.

Forms

Every encoding of FDIV that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FDIV m32fp` FDIV_ST0_MEMmem32real	`D8 /6`	FPU
`FDIV ST(0), st(i)` FDIV_ST0_X87	`D8 F0+i`	FPU
`FDIV m64fp` FDIV_ST0_MEMm64real	`DC /6`	FPU
`FDIV st(i), ST(0)` FDIV_X87_ST0	`DC F8+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(dest) or empty(src):
    underflow()                  # IE, SF, C1 = 0
    dest.write(INDEFINITE)       # the QNaN indefinite
else:
    dest.write(div(dest, src))   # by zero: ZE and an infinity
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 46 cases.

Memory forms

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = div(st0, src)          # a single or double: exact in the
                                 # 80-bit format
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 23 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FDIV m32fp` `FDIV m64fp`
`m32/64fp`	explicit	read
`x87 status word`	implicit	write
`FDIV ST(0), st(i)`
`ST(0)`	explicit	read, write
`st(i)`	explicit	read
`x87 status word`	implicit	write
`FDIV st(i), ST(0)`
`st(i)`	explicit	read, write
`ST(0)`	explicit	read
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

The AT&T names#

Edge cases#

Speed#