FDIVR instruction (x87)

FDIVR divides with the operands the other way round from FDIV: the destination receives the source divided by the destination. fdivr st, st(i) computes ST(i) / ST(0) into ST(0), fdivr st(i), st computes ST(0) / ST(i) into ST(i), and the memory forms divide the single or double by ST(0). FDIVRP does the same into ST(i) and pops, and FIDIVR divides an integer. FDIV’s page covers the precision control, the speed and the AT&T names, which swap the R in the forms with ST(i) as destination; FSUBR’s page shows how the encoding pairs the forms.

The destination is the divisor

Every check that FDIV makes on its divisor, FDIVR makes on its destination. A zero in ST(0) with fdivr st, st(i) or a memory operand is a division by zero: ZE, and with it masked an infinity. Zen 5, with ZE unmasked, left ST(0) = +0 alone for 1 / +0 and raised #MF at the next waiting instruction. Zero over zero, through fdivr st(0), st as well, is invalid: IE and, masked, the QNaN indefinite.

Where compilers use it

A reciprocal or a constant over a variable puts the variable second, and the x87 order of loads makes that a reversed division:

1.0L / x on a long double is FLD of x, FLD1 and fdivrp st(1), st in GCC 14 and Clang 23 at -O2;
*c / x with a double in memory is FLD of x and fdivr qword ptr [rdi];
*n / x with an int is FIDIVR in Clang, and FILD with FDIVP in GCC;
with -m32 -march=i386, GCC divides a double in memory by an integer with FILD of the integer and FDIVR of the double.

Overflow left on the stack

With OE unmasked, Zen 5 divided the largest finite value by 0.5, kept the result in ST(0) with its exponent reduced by 24576 and its significand intact, set OE, and raised #MF at the next waiting instruction. Intel’s manual describes this scaling so that a handler can rescale the value; with OE masked the result would be an infinity or the largest finite value, by the rounding mode. AMD’s Zen 5 guide lists FDIVR like FDIV: one macro-op on pipe FP1, a new one every five cycles at most.

Forms

Every encoding of FDIVR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FDIVR m32fp` FDIVR_ST0_MEMmem32real	`D8 /7`	FPU
`FDIVR ST(0), st(i)` FDIVR_ST0_X87	`D8 F8+i`	FPU
`FDIVR m64fp` FDIVR_ST0_MEMm64real	`DC /7`	FPU
`FDIVR st(i), ST(0)` FDIVR_X87_ST0	`DC F0+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(dest) or empty(src):
    underflow()                  # IE, SF, C1 = 0
    dest.write(INDEFINITE)       # the QNaN indefinite
else:
    dest.write(div(src, dest))   # reversed: the source divided by
                                 # the destination
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 26 cases.

Memory forms

if empty(st0):
    underflow()                  # IE, SF, C1 = 0
    st0 = INDEFINITE
else:
    st0 = div(src, st0)          # the single or double over ST(0)
c0 = c2 = c3 = UNDEFINED

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FDIVR m32fp` `FDIVR m64fp`
`m32/64fp`	explicit	read
`x87 status word`	implicit	write
`FDIVR ST(0), st(i)`
`ST(0)`	explicit	read, write
`st(i)`	explicit	read
`x87 status word`	implicit	write
`FDIVR st(i), ST(0)`
`st(i)`	explicit	read, write
`ST(0)`	explicit	read
`x87 status word`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	M	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

The destination is the divisor#

Where compilers use it#

Overflow left on the stack#