x86-64.net

Instruction

FEMMS

Marks every x87 register empty at the end of 3DNow! or MMX code, exactly as EMMS does; AMD keeps it for older software.

An AMD extension: Intel processors never had it, and in XED's chip model no AMD processor after K10 has it either.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

FEMMS, 0F 0E, is the 3DNow! version of EMMS: it ends MMX or 3DNow! code by tagging all eight x87 registers empty, so that x87 code can run again. Its name stands for Fast Exit Multimedia State, but AMD’s manual gives the two the same function and keeps FEMMS for compatibility with older AMD processors; code meant for any x86 processor should use EMMS, which Intel’s processors have too, while FEMMS raises #UD on every processor without 3DNow!. The page of EMMS explains why the tags matter and what Zen 5 does with EMMS.

3DNow! is gone

FEMMS needs the 3DNow! bit of CPUID, leaf 80000001H, EDX bit 31. AMD’s manual no longer recommends any 3DNow! instruction and names a replacement for each, EMMS for FEMMS; the 3DNow! extension describes the rest. The prefetches that came with it, PREFETCH and PREFETCHW, have a bit of their own and outlived it.

The Zen 5 behind this site’s recorded cases does not report 3DNow!, and both of its FEMMS cases raised #UD: one with three x87 registers in use, one with all eight in use as MMX code leaves them. Each left the tag word, TOP and the registers as they were, so a program that runs FEMMS there to end MMX code gets a fault, not an empty stack.

In compiled code

GCC 14 still accepts -m3dnow and compiles _m_femms() from <mm3dnow.h> to FEMMS, in 64-bit code too, where it also keeps 3DNow! arithmetic such as _m_pfadd on the MMX registers. Clang 23 says that it does not support -m3dnow, and its <mm3dnow.h> warns that the 3DNow! intrinsics are unsupported and no longer declares them; its assembler still takes femms in inline assembly and encodes it as 0F 0E. For new code, EMMS (_mm_empty()) is the instruction to use.

Forms

Every encoding of FEMMS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
FEMMS FEMMS0F 0E3DNow

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[3]
if not features >> 31 & 1:
    fault(UD)                        # CPUID: no 3DNow!
ftw = 0xFFFF                         # every register empty, its value
                                     # kept
top = 0                              # as EMMS does on Zen 5

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no 3DNow!, and every one raised an exception.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
3DNOW

3DNow
CPUID.80000001H:EDX[31] 3DNow

K10 (Family 10h)

More 3DNow! instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. AMD64 Architecture Programmer's Manual, Volume 5: 64-Bit Media and x87 Floating-Point Instructions (26569, rev. 3.16, November 2021), Wayback Machine copy of AMD's PDF
  3. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.