FFREE instruction (x87)

FFREE ST(i) tags one x87 register as empty, and does nothing else. The register keeps its bits and TOP stays where it was, so FFREE is not a pop: after ffree st(0) the top of the stack is an empty register, and the next instruction that reads ST(0) finds a stack underflow. It is two bytes, DD C0+i.

Emptying without reading

FFREE never looks at the value, and an empty register is no error for it: on Zen 5, FFREE of an empty ST(1) or ST(3) raised nothing and changed no tag. That makes it the safe way to clear a register whose state is unknown, where the usual ways read it first:

fstp st(0) pops ST(0) by storing it onto itself, the idiom GCC 14 and Clang 23 at -O2 emit to drop a long double result nobody uses. On an empty ST(0) it is a stack underflow.
FNINIT empties all eight, but resets the control word as well.

ffree st(7) makes room for one more push on a stack that may be full: with eight values loaded, Zen 5 tagged ST(7)’s register empty and left the other seven, so a following FLD cannot overflow. FFREE followed by FINCSTP frees ST(0) and moves TOP like a pop. FFREEP, DF C0+i, does both in one instruction, but neither manual lists it.

Status and waiting

Both manuals leave C0 to C3 undefined. In all six of Zen 5’s cases FFREE cleared C1 and kept C0, C2 and C3. FFREE raises no floating-point exception, but it is a waiting instruction: Intel’s manual lists #MF for a pending unmasked exception, which it delivers before freeing anything.

AMD’s Zen 5 guide lists FFREE as one macro-op, six per cycle, with no FP pipe named for it.

Forms

Every encoding of FFREE that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FFREE st(i)` FFREE_X87	`DD C0+i`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

free(src)                            # its tag only: it keeps its value,
                                     # and TOP stays
c0 = c1 = c2 = c3 = UNDEFINED        # Zen 5 clears C1

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FFREE st(i)`
`st(i)`	explicit	read
`x87 tag word`	implicit	write

Flags

U undefined; blank: not affected. How to read.

C0	C1	C2	C3
All forms
U	U	U	U

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions

Emptying without reading#

Status and waiting#