FICOMP instruction (x87)

Forms

Every encoding of FICOMP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`FICOMP m32int` FICOMP_ST0_MEMmem32int	`DA /3`	FPU
`FICOMP m16int` FICOMP_ST0_MEMmem16int	`DE /3`	FPU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if empty(st0):
    underflow()
    x = 3                            # unordered
else:
    x = comi(st0, signed(src))       # the integer, exactly; any NaN
                                     # raises IE
c3 = x in (2, 3)                     # set with IE or DE unmasked too
c2 = x == 3
c0 = x in (1, 3)
c1 = 0
pop()                                # not with IE or DE unmasked

Run on AMD Zen 5 (EPYC 9645): 18 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`FICOMP m16int` `FICOMP m32int`
`m16/32int`	explicit	read
`x87 register stack`	implicit	pop
`x87 status word`	implicit	write

Flags

M modified; blank: not affected. How to read.

C0	C1	C2	C3
All forms
M	M	M	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`X87` x87	FPU `CPUID.01H:EDX[0]` FPU	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More x87 instructions

All 90 x87 instructions